Apple A9X: A Closer Look At The Powerful Chipset That Delivers The Final Blow To Its Competition

Omar Sohail
Posted 11 months ago

Apple A9X is the company’s first dedicated developed chipset that has been manufactured on the FinFET process and is only present in the 12.9 inch iPad Pro. Let us take a closer look at how the SoC is able to deliver such astounding amounts of power.


Apple A9X; Die size And Other Details

According to Chipworks, A9X measures in at 147mm2 and their sample shows that it has been manufactured on the 16nm FinFET process. Similar to Apple’s iPhone 6s and iPhone 6s Plus, it should be noted that while Chipworks was only able to get its hands on one sample, so there could be another manufacturer making small volumes of chips for the tech giant. It should also be noted that the die is only second largest from the X-series of SoCs. The only chipset that is larger in size in comparison to this one is A5X.

Chipset comparison detailsA9XA9A8X
CPU type2 Twister cores 2 Twister cores 3 Typhoon cores
Processor speed2.26GHz 1.85GHz1.5GHz
GPU detailsPowerVR 12 Cluster Series7 PowerVR GT7600 PowerVR GXA6850
Memory Bus Width128 bits64 bits128 bits
Memory bandwidth51.2GB/sec 25.6GB/sec 25.6GB/sec
L2 Cache 3MB 3MB 2MB
L3 Cache N/A4MB 4MB


Another thing that we want to add here is that Apple’s A9X is larger compared to Intel’s Skylake processors. Their die sizes have been detailed below:

  • Skylake-Y: 99mm2 for the 2 core GT2 configuration
  • Skylake-K: 122mm2 for the 4 core desktop GT2 configuration

The Graphics Processor: What Latest Addition Has Apple Incorporated?

One thing that we can agree on is that Apple invested quite a bit on the die space in order to improve graphics performance on a larger scale. While the company’s A9 packs 6 GPU cores, the flagship SoC features 12 GPU cores, delivering twice the amount of graphical performance that A9’s GPU will be capable of.

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This would also explain why the RAM found is LPDDR4 and functions at the 128 bit bus width. With twice the number of cores compared to A9, Apple would need twice as much memory bandwidth to maintain the same bandwidth-to-core ratio, which also explains the answer why A9X is able to deliver twice the memory bandwidth as compared to A9.


L3 Cache: Surprisingly, There Is None Of It. Why Not?

One of the most surprising changes that we have seen in A9X is the absence of L3 cache. Now why would Apple make such a move like that? The only cache to be found on A9X are the L1 and L2 caches for the CPU and GPU respectively, along with some even smaller amounts for cache for various other functional blocks.


One primary reason that comes to mind is that the company no longer deemed L3 cache a necessity thanks to the 51.2GB/sec memory bandwidth present thanks to the existence of high RAM LPDDR4 memory and high memory bus width. However, while L3 would have cost Apple a slight amount, it would have caused negligible change to the die size, so it is possible that company omitted this variable from the equation since it would ended up increasing the iPad Pro’s overall power draw.

From what we have seen so far, it appears that adding L3 cache would have absolutely no effect since A9X has dominated fiercely in the performance charts, putting Apple on top once more.


Are we going to see a significant reply from other SoC manufacturers other there? We certainly will, but in due time.

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