AMD Reportedly Planning Zen 4 EPYC Genoa CPUs With HBM Memory To Tackle Intel Sapphire Rapids Xeons

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Intel may not be the only chip maker to offer HBM powered server CPUs as AMD is reportedly planning its own EPYC Genoa variants based on the Zen 4 architecture for bandwidth-bound workloads.

AMD To Answer Intel's Sapphire Rapids Xeon CPUs With Its Own HBM Powered Zen 4 EPYC Genoa CPUs, Alleges Rumor

The rumor comes from Inpact-Hardware who have reportedly received information from their sources that AMD is planning an HBM variant of its upcoming EPYC Genoa CPUs powered by the Zen 4 core architecture. While we have learned much about the standard Genoa CPUs, this is the first time we are hearing of an HBM variant.

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There is indeed a recurring question of an HBM version of Zen 4 among partners, but for the moment nothing seems definitively decided on this subject. The manufacturer could indeed reserve such a solution for certain customers or ultimately prefer a variation with 3D V-Cache .

via Inpact-Hardware

According to the report, an EPYC CPU with HBM memory is a recurring question among AMD's partners. Intel has already announced its HBM variant of Sapphire Rapids though those chips aren't expected around 2023 (in volume). AMD is reportedly preparing its Milan-X lineup as an intermediate between Zen 3 and Zen 4 which would house 3D chip stacking technology though nothing is clear whether the die stacking is based around CCD's or V-Cache (similar to next-gen Ryzen Zen 3 Desktop CPUs).

It is likely that AMD could offer Milan-X with 3D V-Cache as a showcase of how the low-level cache can help boost performance in bandwidth-bound workloads and ultimately scale it up with more premium HBM options when EPYC Genoa launches. The difference between Milan and Milan-X in terms of launch is around 2-3 quarters and the same timeframe can be expected for an AMD EPYC Genoa lineup with HBM.

What's definitely going to be interesting is AMD's HBM implementation as they can go with either traditional off-die methods or a more next-gen 3D Chip stacking tech. Intel hasn't confirmed what solution it will use for its HBM integration but they are most likely going to utilize their EMIB and Forveros interconnect/packaging technologies to integrated HBM memory on Xeon CPUs. It will be great to see both companies offer HBM server variants to expand their workload portfolio in the HPC segment.

AMD EPYC CPU Families:

Family BrandingEPYC 7007?EPYC 7006?EPYC 7004?EPYC 7005?EPYC 7004?EPYC 7004?EPYC 7003X?EPYC 7003EPYC 7002EPYC 7001
Family Launch2025+2024-2025?20232023202320222022202120192017
CPU ArchitectureZen 6?Zen 5Zen 4Zen 4CZen 4 V-CacheZen 4Zen 3Zen 3Zen 2Zen 1
Process NodeTBD3nm TSMC?5nm TSMC5nm TSMC5nm TSMC5nm TSMC7nm TSMC7nm TSMC7nm TSMC14nm GloFo
SocketTBDLGA 6096 (SP5)
LGA 4844LGA 6096LGA 6096LGA 6096LGA 4094LGA 4094LGA 4094LGA 4094
Max Core Count384?25664128969664646432
Max Thread Count768?51212825619219212812812864
Max L3 CacheTBDTBD256 MB?TBD1152 MB?384 MB?768 MB?256 MB256 MB64 MB
Chiplet DesignTBDTBD8 CCD's (1CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (2 CCX's per CCD) + 1 IOD4 CCD's (2 CCX's per CCD)
Memory SupportTBDDDR5-6000?DDR5-5200DDR5-5600?DDR5-5200DDR5-5200DDR4-3200DDR4-3200DDR4-3200DDR4-2666
Memory ChannelsTBD12 Channel (SP5)
6-Channel (SP6)
6-Channel12 Channel12 Channel12 Channel8 Channel8 Channel8 Channel8 Channel
PCIe Gen SupportTBDTBD96 Gen 5160 Gen 5160 Gen 5160 Gen 5128 Gen 4128 Gen 4128 Gen 464 Gen 3
TDP RangeTBD480W (cTDP 600W)70-225W320W (cTDP 400W)200W (cTDP 400W)200W (cTDP 400W)280W280W280W200W
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