AMD is allegedly stated to offer a brand new lineup of X3D MCM chips within its 3rd Gen EPYC Milan CPU stack which will be unlike anything they have done before. These new processors are seemingly going to be known as Milan-X and will be the next step in the evolution of AMD's CPUs using next-generation packaging technologies.
AMD EPYC Milan-X CPUs To Feature X3D Packaging Technology For Stacked Zen 3 Chiplets
We did hear a rumor a while back that AMD was working on an intermittent EPYC Refresh based on its Zen 3 core architecture. The lineup was suggested to be a part of the Milan lineup with the Zen 3 CPU cores but little was known at the moment. It looks like Patrick Schur & ExecutableFix, both of who happen to be very reliable leakers and insiders, have got the first information on what AMD's next-gen EPYC parts are going to be.
Milan-X aka Milan-X(3D). Genesis IO-die with stacked chiplets
I love lasagna 😋 https://t.co/O2FrGxyd8P
— ExecutableFix (@ExecuFix) May 25, 2021
In their latest tweet, it is stated that AMD is working on a new CPU which is codenamed Milan-X. This is the first time we have heard of such a name but since Milan is part of the EPYC family, the chip will definitely be aimed at the server market. The other detail is that the Milan-X CPUs will be utilizing stacked dies. This is X3D packaging in specific and the stacking will be for the Zen 3 CCD's while the Genesis IOD will still be onboard the chips.
It's been a while since AMD talked about 3D Packaging on its CPUs but back at its Financial Analyst Day in 2020, AMD showcased a slide in which it showed a hybrid 2.5D & 3D packaged design that comprised of various chiplets. The mockup showcased by AMD had four compute and four stacked dies with each stack comprising of four chips.
Now we have already seen a mockup of AMD's next-generation EPYC Genoa parts which showcase a standard MCM package design comprising 12 Zen 4 and 1 IOD so it's likely that the Milan-X chips will be produced for a very niche use case. AMD did highlight bandwidth density as a main feature of the X3D packaged chips so it could be aimed at servers and HPC workloads which demand large bandwidth.
Now here's a bit of speculation, since AMD is already invested in X3D packaging for its top-tier EPYC chips, it is the conclusive path for Zen 4 to follow the same as it is the next fundamental step in AMD's packaging roadmap. We recently saw a mockup of Raphael, AMD's next-generation Ryzen mainstream CPUs and while the package size makes it hard to incorporate more than 3 chiplets, a possibility exists that we might see an X3D solution on mainstream parts, packing up to 4 Zen 4 CCD's for a total of 32 core and 64 threads. It is also possible that after Milan-X, future AMD EPYC lineups will incorporate both standard MCM and X3D SKUs but that remains to be seen. As for the launch, it is likely that we may see the X3D chips around late 2021 or early 2022 (but only on paper).
AMD EPYC CPU Families:
|Family Name||AMD EPYC Venice||AMD EPYC Turin||AMD EPYC Siena||AMD EPYC Bergamo||AMD EPYC Genoa-X||AMD EPYC Genoa||AMD EPYC Milan-X||AMD EPYC Milan||AMD EPYC Rome||AMD EPYC Naples|
|Family Branding||EPYC 7007?||EPYC 7006?||EPYC 7004?||EPYC 7005?||EPYC 7004?||EPYC 7004?||EPYC 7003X?||EPYC 7003||EPYC 7002||EPYC 7001|
|CPU Architecture||Zen 6?||Zen 5||Zen 4||Zen 4C||Zen 4 V-Cache||Zen 4||Zen 3||Zen 3||Zen 2||Zen 1|
|Process Node||TBD||3nm TSMC?||5nm TSMC||4nm TSMC||5nm TSMC||5nm TSMC||7nm TSMC||7nm TSMC||7nm TSMC||14nm GloFo|
|Platform Name||TBD||SP5 / SP6||SP6||SP5||SP5||SP5||SP3||SP3||SP3||SP3|
|Socket||TBD||LGA 6096 (SP5)|
LGA XXXX (SP6)
|LGA 4844||LGA 6096||LGA 6096||LGA 6096||LGA 4094||LGA 4094||LGA 4094||LGA 4094|
|Max Core Count||384?||256||64||128||96||96||64||64||64||32|
|Max Thread Count||768?||512||128||256||192||192||128||128||128||64|
|Max L3 Cache||TBD||TBD||256 MB?||TBD||1152 MB?||384 MB?||768 MB?||256 MB||256 MB||64 MB|
|Chiplet Design||TBD||TBD||8 CCD's (1CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD||8 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's (2 CCX's per CCD) + 1 IOD||4 CCD's (2 CCX's per CCD)|
|Memory Channels||TBD||12 Channel (SP5)|
|6-Channel||12 Channel||12 Channel||12 Channel||8 Channel||8 Channel||8 Channel||8 Channel|
|PCIe Gen Support||TBD||TBD||96 Gen 5||160 Gen 5||160 Gen 5||160 Gen 5||128 Gen 4||128 Gen 4||128 Gen 4||64 Gen 3|
|TDP Range||TBD||480W (cTDP 600W)||70-225W||320W (cTDP 400W)||200W (cTDP 400W)||200W (cTDP 400W)||280W||280W||280W||200W|