New details have started to pop up on AMD’s Next Generation Trinity APU’s (Accelerated Processing Units) which would launch in early 2012. According to Semiaccurate, AMD would showcase their next generation Trinity chips at the CES 2012 or the Fusion 2012 Developer Summit (CES 2012).
Other than the release date, A Chinese forum member has leaked new slides which detail new specs and socket compatibility for the new chips. We all know that the Trinity APU’s would be based on the Piledriver core (2nd Generation Bulldozer core) which offer upto 30% increase in Performance over past gen Llano Fusion chips. Turbo Core 3.0 speeds would also be relatively better ranging from 300 – 900Mhz depending on the base clock speeds and the A75 chipset still exists in the new boards.
However, The A1 ES Revision of the chips show that the TDP would be around the 125W level against the 100/65W of the Llano chips. This could be due to the use of 32nm Bulldozer architecture and Quad Core designs along with the use of 4Mb L2 cache while no L3 Cache is available.
Also recent exposure of an Trinity Engineering Sample APU has showed that the FM2 socket won’t be backwards compatible with Llano chips neither would the Trinity APU’s be with FM1 socket. This is because of one less pin on the FM2 socket which makes the use of llano on the socket impossible, Following pictures show the difference in between both sockets and chips:
Also, It was previously rumored that Trinity might feature an IGP based on the GNC HD7000 GPU but it has been confirmed that Trinity would only feature the HD7000 Series chips with the VLIW4 architecture. More on AMD’s Trinity APU below: