It's been a while since we last heard about Intel's 2020 Xeon CPU family which will include Ice Lake-SP and Cooper Lake-SP lineups. Today, there are new details to talk about regarding both lineups as revealed in the latest slides by tech leakers Komachi and Momomo_US. The reported slides are from an internal briefing on Intel's Barlow Pass, 2nd Generation Optane DC Persistent memory & the other are from CISCO which lists down a few Xeon 2S blade servers configurations.
Intel 2020 Xeon CPU Family Detailed - 2S Ice Lake-SP & Cooper Lake-SP Get 8 Channel Memory on Whitley & 4S Cooper Lake-SP Gets 6 Channel Memory on Cedar Island Platform
Intel faces some serious competition in 2020 as AMD gets ready to launch its 3rd Generation EPYC platform by the end of this year. Intel, on the other hand, would be introducing two key lineups in its Xeon family, the 14nm Cooper Lake, and the 10nm Ice Lake. Intel's 2020 Xeon family had to be pushed back as reported earlier which means that they will be pitted right against AMD's 3rd Gen EPYC Milan CPUs based on the new Zen 3 core architecture. There have been recent performance leaks for the Xeon family which show some hopeful results but we have to wait and see what Intel really has in its hands for the Server, HPC and Data Center segment.
With that said, let's talk about what Intel has planned out for its 2020 Xeon lineup. The Intel 2020 lineup would come in two distinct platforms, one is called Cedar Island and the other is known as Whitley. Whitley would come in as a 2-Socket configuration for both Cooper Lake-SP and Ice Lake-SP processors. The Cedar Island platform, on the other hand, will enable 4-Socket configurations but would only feature Cooper Lake-SP CPUs.
As illustrated in the diagram above, the Whitley platform would feature 8 channel memory. From previously leaked slides, it was reported that Ice Lake-SP and Cooper Lake-SP would get 8-channel memory on the Whitley platform but the slide above shows Ice Lake chips specifically featuring four 2 channel IMCs whereas we Cooper Lake-SP on Cedar Island only features two 3-channel IMCs. It is highly likely that Cooper Lake-SP configurations for Whitley would get the same 4x2-channel IMC configuration as Ice Lake-SP and it's just not shown here.
The 2nd Gen Optane DC Persistent memory would be supported on both platforms (Barlow Pass), offering up to 3200 MT/s and 15% bandwidth improvement in a 15W DIMM. Whitley would be able to support up to 3200 MT/s and 4 TB capacity per socket whereas Cedar Island would feature 2933 MT/s speeds and 3 TB capacity per socket. It is also stated that Barlow Pass DIMMs would feature a new blue-colored DIMM heat spreader for better identification in the data center. With the Xeon 2020 platforms detailed, the following is a look at what to expect from the Xeon CPU lineups.
Intel Xeon 10nm+ Ice Lake-SP/AP Family
Intel Ice Lake-SP processors will be available in the third quarter of 2020 and will be based on the 10nm+ process node. We have seen earlier slides say that the Ice Lake family would feature up to 28 cores but the one from ASUS's presentation says that it would actually feature up to 38 cores & 76 threads per socket.
The main highlight of Ice Lake-SP processors will be support for PCIe Gen 4 and 8-channel DDR4 memory. The Ice Lake Xeon family would offer up to 64 PCIe Gen 4 lanes and would offer support for 8-channel DDR4 memory clocked at 3200 MHz (16 DIMM per socket with 2nd Gen Persistent memory support). Intel Ice Lake Xeon processors would be based on the brand new Sunny Cove core architecture which delivers an 18% IPC improvement versus the Skylake core architecture that has been around since 2015.
One thing to note is that Intel's 10nm for 2020 is an enhanced node of the original 10nm node that will launch this year. It's marked as 10nm+ and that is specifically what the Ice Lake-SP Xeon line will make use of. Some of the major upgrades that 10nm will deliver include:
- 2.7x density scaling vs 14nm
- Self-aligned Quad-Patterning
- Contact Over Active Gate
- Cobalt Interconnect (M0, M1)
- 1st Gen Foveros 3D Stacking
- 2nd Gen EMIB
Intel Xeon 14nm+++ Cooper Lake-SP/AP Family
Moving on to the Intel Cooper Lake Xeon CPU family which is based on the 14nm+++ process node, we are looking at up to 48 cores and 96 threads in a socketed design. The current Cascade Lake-SP family offers up to 28 cores in socketed variants while the Cascade Lake-AP SKUs which come in BGA only, offer up to 56 cores and 112 threads with TDPs as high as 400W.
There will also be a 56 core and 112 thread socketed variant in the Cooper Lake family but that is likely to be part of the Xeon-AP line of chips which feature two dies on the same interposer. In a similar fashion, the BGA and LGA parts in the Ice Lake-AP family could also feature more cores than the SP part but they will be dual-die design and not a single monolithic chip like the ones mentioned here. Also, the 38 core configuration for Ice Lake Xeon doesn't make sense since that means there have to be two 19 core dies and the 19 core config itself isn't something that Intel has done before.
In addition to the higher core count, Intel's Cooper Lake line of Xeon Scalable processors is said to offer higher memory bandwidth, higher AI inference & training performance while supporting blfloat16 through Intel's DL Boost framework. The Whitley platform which will be based around the LGA 4189 socket will also feature support for Intel's Ice Lake-SP processors that utilize the 10nm process node. Ice Lake-SP will also launch in 2020, just slightly after the introduction of Cooper Lake-SP. The Whitley platform would offer support for 8 channel DDR4 memory, 64 PCIe Gen 3.0 lanes.
Intel Xeon SP Families (Preliminary):
|Family Branding||Skylake-SP||Cascade Lake-SP/AP||Cooper Lake-SP||Ice Lake-SP||Sapphire Rapids||Emerald Rapids||Granite Rapids||Diamond Rapids|
|Process Node||14nm+||14nm++||14nm++||10nm+||Intel 7||Intel 7||Intel 3||Intel 3?|
|Platform Name||Intel Purley||Intel Purley||Intel Cedar Island||Intel Whitley||Intel Eagle Stream||Intel Eagle Stream||Intel Mountain Stream|
Intel Birch Stream
|Intel Mountain Stream
Intel Birch Stream
|Core Architecture||Skylake||Cascade Lake||Cascade Lake||Sunny Cove||Golden Cove||Raptor Cove||Redwood Cove?||Lion Cove?|
|IPC Improvement (Vs Prev Gen)||10%||0%||0%||20%||19%||8%?||35%?||39%?|
|MCP (Multi-Chip Package) SKUs||No||Yes||No||No||Yes||Yes||TBD (Possibly Yes)||TBD (Possibly Yes)|
|Socket||LGA 3647||LGA 3647||LGA 4189||LGA 4189||LGA 4677||LGA 4677||TBD||TBD|
|Max Core Count||Up To 28||Up To 28||Up To 28||Up To 40||Up To 56||Up To 64?||Up To 120?||Up To 144?|
|Max Thread Count||Up To 56||Up To 56||Up To 56||Up To 80||Up To 112||Up To 128?||Up To 240?||Up To 288?|
|Max L3 Cache||38.5 MB L3||38.5 MB L3||38.5 MB L3||60 MB L3||105 MB L3||120 MB L3?||240 MB L3?||288 MB L3?|
|Memory Support||DDR4-2666 6-Channel||DDR4-2933 6-Channel||Up To 6-Channel DDR4-3200||Up To 8-Channel DDR4-3200||Up To 8-Channel DDR5-4800||Up To 8-Channel DDR5-5600?||Up To 12-Channel DDR5-6400?||Up To 12-Channel DDR6-7200?|
|PCIe Gen Support||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 4.0 (64 Lanes)||PCIe 5.0 (80 lanes)||PCIe 5.0 (80 Lanes)||PCIe 6.0 (128 Lanes)?||PCIe 6.0 (128 Lanes)?|
|TDP Range (PL1)||140W-205W||165W-205W||150W-250W||105-270W||Up To 350W||Up To 375W?||Up To 400W?||Up To 425W?|
|3D Xpoint Optane DIMM||N/A||Apache Pass||Barlow Pass||Barlow Pass||Crow Pass||Crow Pass?||Donahue Pass?||Donahue Pass?|
|Competition||AMD EPYC Naples 14nm||AMD EPYC Rome 7nm||AMD EPYC Rome 7nm||AMD EPYC Milan 7nm+||AMD EPYC Genoa ~5nm||AMD EPYC Bergamo||AMD EPYC Turin||AMD EPYC Venice|
CISCO has also talked about its B200 M6 blade server rack which would feature up to two Cooper Lake-SP CPUs, 32 DDR4 DIMM slots, up to 80 Gbps I/O (Bodega) interconnect, up to 2x 7mm NVMe or SATA drives, up to 2 microSD cards, an NVIDIA P6 tier GPU and up to 2 M.2 NVMe drives. The server is optimized as a 2S configuration and hence is based on the Whitley platform but Cooper Lake-SP only gets PCIe Gen 3 support which is clearly stated in the presentation.
Intel's Sapphire Rapids-SP and Granite Rapids-SP Xeon families for the Eagle Stream platform were also detailed a while back and would bring on the post 10nm era for Intel's Xeon segment, offering new capabilities such as PCIe 5.0 and DDR5 memory along with the new Golden and Willow Cove cores that are expected to further leverage Intel's IPC lead in the server market. You can read more here.
The Xeon Scalable family was very recently refreshed, further confirming the reports of delays we heard regarding Intel's Cooper Lake and Ice Lake Xeon CPUs which have been pushed back by up to 3 months due to various instability issues. This would further increase the pressure on Intel as their 10nm and 14nm Xeon processors would be directly competing against AMD's 7nm+ EUV based EPYC Milan lineup which is going to feature the brand new Zen 3 core architecture which is confirmed to be one of AMD's biggest architectural upgrade since the original Zen core.