NVIDIA Vera CPU Is Architected For The Agentic AI Era, as It Delivers Max Single-Core & Single-Thread Performance Versus x86; Full Architectural Breakdown Shows

The NVIDIA Vera CPU is designed for Reinforcement Learning and Agentic AI systems, offering 88 Olympus cores for max single-core performance.

NVIDIA's x86-Killer, Vera CPU, Is Now Available, Built Purely With Agentic AI In Mind

Surge in agentic AI workloads and reinforcement learning emerging as a key scaling mechanism for improving model capability have made CPUs a vital component for AI systems. Without a fast CPU (execution, evaluation, orchestration), a GPU won't be able to be supplied with context, and that leads to major drawbacks and inefficiencies. This is why NVIDIA designed Rubin, a CPU that is purpose-built for agents, and a chip that eliminates these bottlenecks, delivering the throughput and efficiency that the industry demands.

Learn more about NVIDIA's Vera CPU performance over here!

Today, we will give you a full rundown of Vera, NVIDIA's latest and greatest CPU for AI, based on custom Arm cores.

The Insides of The Vera CPU

On a high-level, NVIDIA's Vera CPU is based on the Olympus Core architecture, which utilizes the custom Armv9.2 IP. It is based on a monolithic compute die and comes with technologies such as 2nd Gen NVIDIA Scalable Coherency Fabric (SCF), Confidential Computing (TEE-I/O Capable), and x16 PCIe Gen6 CXL 3.1.

Key benefits of the NVIDIA Scalable Coherency Fabric include:

• Low-latency communication between CPU clusters
• Efficient access to shared system-level cache resources
• High-bandwidth connectivity to memory controllers
• Native integration with NVLink-C2C and accelerator infrastructure

The Brand Prediction features Neural & Special-Purpose Predictors with 2 taken branchers per cycle. It has a 10-Wide Instruction Decode, a Novel Graph and Advanced Prefetcher, 96 KB of L1D, 64 KB of L1I, 2 MB of L2, and 164 MB of L3 cache. Each core has access to 14 GB/s of bandwidth. The NVLink C2C interconnect offers up to 1.8 TB/s of coherent CPU-GPU bandwidth.

In total, there are 88 Olympus "high-performance" cores and 176 NVIDIA Spatial Multi-threading threads on Vera. The chip integrates a wide, high-IPC microarchitecture that is designed to offer maximum single-threaded performance, achieving efficient concurrency across thousands of software environments.

Cores / Threads	88 / 176
L2 cache	2 MB per core
L3 cache	164 MB per CPU
Memory	Up to 1.5 TB SOCAMM2 LPPDDR5X
Memory speed	Up to 9600 MT/s
Memory bandwidth	Up to 1.2 TB/s (aggregate), 14 GB/s (per core)
PCIe	88 PCIe 6.4 lanes (CPU only), 96 PCIe 6.4 lanes (Vera Rubin), bifurcation down to x2, CXL 3.1
Configurable TDP	250W - 450W

Olympus - The AI Peak

Olympus, the core powering Vera, is referred to as the compute engine of the CPU. It is built from the ground up with one goal: to maximize IPC (Instructions Per Cycle) for irregular, branch-heavy, latency-sensitive, and highly concurrent software. Versus Grace, Vera achieves a 50% gain in IPC. There are four key components of the Vera CPU architecture:

• Front End: Optimized Branch Predictors
• Mid Core: Critical Path Acceleration
• Execution Engine: Complex Vector Optimization
• Cache Subsystem: Latency-Optimized Instruction and Data Paths

The following is the block diagram of the Olympus core:

Olympus Neural Branch Predictor

Starting with the dissection of the Olympus core, we first have the Neural Branch Predictor, which is designed to improve prediction accuracy on complex, branch-heavy software.

The NBP learns longer-range control-flow behavior and statistically biased branch patterns that are common in large runtime environments, interpreters, databases, compilers, and agent workloads. The branch prediction improvements allow Olympus's front end to be supplied with useful instructions, which in turn enable higher instruction throughput and more consistent performance.

Olympus Mid-Core

The Mid Core on Olympus turns decoded instructions into executable operations while maxing instruction-level and memory-level parallelism. The Olympus Mid Core is designed to identify and execute independent work hidden behind these bottlenecks, enabling higher utilization of execution resources and improved overall IPC.

Mid Core comes with a wide rename and allocation engine that is supported by a large reorder buffer and extensive physical register resources. The Mid Core Register renaming eliminates false dependencies between instructions, allowing the processor to expose additional parallelism and execute instructions as soon as their true operands become available. A large instruction window enables Olympus to look significantly further ahead in the instruction stream, finding useful work while other instructions wait on memory or branch resolution.

Olympus also houses several technologies to break dependencies, such as:

• Memory Renaming: Accelerates store-to-load dependency chains by allowing dependent instructions to execute before a load completes when the data relationship can be predicted or determined. This is particularly beneficial for pointer-heavy software, graph traversal, runtime frameworks, and complex object-oriented workloads.
• Value Prediction: Identifies stable dependency chains and predicts future values before they are produced, allowing dependent instructions to execute speculatively while correctness is verified later. This capability is especially effective for repetitive software patterns and sequential data structures.
• Move elimination and value optimization: Techniques to achieve higher utilization.

Olympus Execution Engine

The execution engine within the Olympus core is designed to sustain high instruction throughput across various workloads, including Agentic AI runtimes, RL environments, databases, and more. After the instructions pass through the rename and scheduling stages, they are dynamically dispatched to specialized execution resources optimized for integer arithmetic, branch processing, vector computation, and memory operations.

The combination of a wide execution backend and deep out-of-order engine allows Olympus cores to continue making progress even when some parts of the workloads are slowed down by memory access, branch resolution, or long dependency chains.

So for the Execution Engine, NVIDIA packs 8 simple Integer ALUs, 2 Complex ALUs, and 4 dedicated branch execution units. The simple ALUs handle common arithmetic and logical operations, while the complex ALUs accelerate higher-latency operations such as multiplication, division, CRC, and shift-intensive workloads.

The dedicated branch units work in conjunction with the advanced branch prediction subsystem to rapidly resolve control-flow decisions and minimize pipeline disruption. This combination is particularly beneficial for modern agentic workloads, which often exhibit irregular control flow and frequent branching as agents reason, evaluate state, and execute actions.

For vector and AI-oriented computation, Olympus integrates six 128-bit SVE vector execution units, including two crypto-capable vector pipelines, and supports FP8 precision. These units accelerate vectorized workloads commonly found in data processing, machine learning preprocessing, compression, encryption, scientific computing, and analytics frameworks. Support for Arm Scalable Vector Extension (SVE) enables efficient execution of both traditional HPC workloads and emerging AI data-processing pipelines.

The Execution Engine is tightly integrated with a high-bandwidth memory subsystem through four load pipelines and 2 store pipelines. Together, these resources enable Olympus to maintain high utilization across both compute-intensive and memory-intensive workloads.

Vera's Spatial Multi-Threading Offers Higher Single-Threaded Throughput Than Traditional SMT Approaches

NVIDIA is making use of a new multi-threading solution in Vera CPUs called Spatial Multi-Threading. Compared to traditional SMT (Simultaneous Multi-Threading), the NVIDIA approach makes it so that resources can be partitioned across two hardware threads inside the Olympus core instead of relying primarily on a narrower core.

Traditional SMT achieves this by allowing both hardware threads to opportunistically share the same core resources. In densely threaded sandbox environments, that sharing can create contention across branch prediction, decode, execution, load/store, cache, and memory resources. This creates a “noisy neighbor” effect, where activity on one thread can reduce the performance of the other thread sharing the same core within a sandbox. For agentic AI, reinforcement learning, and cloud services—where many short-running tasks execute concurrently and tail latency matters—this can increase variability and make performance less predictable.

With this, Vera offers a high-throughput single-threaded core when needed, while the thread duo handles management. With 88 cores and 176 threads, NVIDIA's Vera is a flexible CPU that offers both high single-threaded performance and dense vGPU-style deployments.

Spatial Multithreading improves determinism, isolation, and quality of service compared to traditional SMT approaches. The result is a CPU architecture that can run large numbers of concurrent agent tasks while maintaining more consistent latency and throughput.

The Vera Memory Subsystem - LP5X Lowers Power Input Versus DDR DIMMs

NVIDIA went with LPDDR5X memory for its Vera CPUs by fusing the chip with eight controllers, offering up to 1.2 TB/s of bandwidth. The LPDDR5X memory comes with data center-class ECC (Error-Correcting Code) and enables the platform to significantly reduce power consumption vs traditional DDR4-based servers. The chip enables up to 1.5 TB of LPDDR5X capacity.

The use of LPDDR5X memory in the SOCAMM2 form factor also plays a vital role in driving up power efficiency, while the three primary objectives for this memory type include:

• High Bandwidth – Deliver the memory bandwidth required to sustain modern AI, analytics, and HPC workloads.
• Power Efficiency – Maximize bandwidth per watt using LPDDR5X technology to reduce overall platform power.
• Enterprise Serviceability – Provide a modular, field-replaceable memory architecture suitable for hyperscale and enterprise deployments.

The LPDDR5X memory on Vera operates at 9600 MT/s, offering up to 14 GB/s of memory bandwidth to each Olympus core. The memory capacities are fully scalable from 256 GB up to 1.5TB.

Now, the use of LP5X also has a major reason, and that is to drive down the power envelope. Traditional DRAM standards such as DDR5 (DIMM, RDIMM, MRDIMM) do offer higher bandwidth, but they also use much higher power. RDIMM platforms can consume over 100W, while MRDIMM solutions can use over 200W of power in bandwidth-heavy workloads. SOCAMM2, on the other hand, achieves up to 1.2 TB/s speeds while consuming just 30-40W, and that's for a fully-loaded system.

The IOs - PCIe 6.4, 2nd Gen NVLink, Dual-Socket Scale, and Confidential Computing

On the IO, Security and Scale-Up front, NVIDIA Vera CPUs offer lots of technological innovations such as the following:

• Second-Generation NVLink-C2C – High-bandwidth coherent interconnect for CPU-to-GPU and CPU-to-CPU communication.
• Two-Socket Scale-Up – High-speed coherent processor-to-processor connectivity for scalable dual-socket systems.
• PCI Express 6.4 – High-performance I/O connectivity for storage, networking, and accelerator devices.
• Compute Express Link (CXL) 3.1 – Extends the PCIe infrastructure to support memory expansion, pooling, and composable system architectures.
• Confidential Computing - Secure scale-up environment across 2-socket and NVL rack.

Starting with PCIe, Vera leverages the latest PCIe 6.4 standard with each chip offering up to 88 PCIe lanes, while dual-socket configurations offer 176 lanes. These operate at speeds of up to 64 GT/s, doubling the throughput of the PCIe 5 standard, and ensure enough bandwidth for AICs and storage solutions. Vera also comes with a wide array of PCIe lane bifurcation, as detailed in the table below:

Further extension to CXL 3.1 enables next-gen memory expansion and composable infrastructure with the support of CXL Type-3 memory devices beyond the standard LPDDR5X solution.

Vera supports Arm CCA, RME-DA, and RME-CDA, providing the foundation for confidential VM isolation and secure device assignment. Per-VM encryption keys enable cryptographic isolation between tenants running on the Vera CPU, while support for TDISP-capable devices extends the trusted execution environment beyond the CPU.

As the industry’s first Confidential Computing CPU to enable TDISP for coherent devices such as GPUs, Vera provides high-performance, coherent access without bounce buffers or unnecessary data copies while maintaining strong workload isolation. On the security, reliability, and availability front, Vera offers the following:

RAS Feature	Description
Multi-symbol ECC Correction	Corrects multi-symbol memory errors, providing the foundation for enterprise-class memory reliability.
Multi-Bit Correctable Error Reporting	Reports multi-bit correctable ECC events to firmware and the operating system, enabling early diagnostics and proactive maintenance.
RAS Error Records	Implements RAS records for consistent error reporting, diagnostics, and operating system integration.
Hard Post-Package Repair (PPR)	Permanently repairs defective memory locations identified during manufacturing or deployment, improving long-term memory reliability.
Page Offlining	Offlines memory pages that have experienced uncorrectable errors, reducing failure blast radius and improving system availability.
Channel Sparing	Redirects memory accesses away from degraded channels or channel resources, improving platform availability and fault tolerance.
SOCAMM2 Modular Support	Enables field replacement and servicing of memory modules without replacing the processor or motherboard.
Error Injection Support	Provides hardware-assisted error injection to validate firmware, operating system recovery flows, and platform RAS mechanisms.

NVIDIA's Vera CPU represents a groundbreaking advancement in processor design, purpose-built to power the next era of agentic AI and reinforcement learning workloads. Leveraging the innovative Olympus core architecture with custom Armv9.2 technology, Vera delivers exceptional single-threaded performance through a high-IPC microarchitecture featuring advanced neural branch prediction, sophisticated mid-core parallelism techniques like memory and value prediction, a powerful execution engine with vector capabilities, and an optimized cache subsystem.

Its Spatial Multi-Threading approach ensures superior determinism and isolation compared to traditional SMT, while the integration of high-bandwidth LPDDR5X memory, second-generation NVLink-C2C, PCIe 6.4, CXL 3.1, and comprehensive confidential computing features enables seamless CPU-GPU orchestration, massive scalability, and enhanced security.

By eliminating traditional bottlenecks in execution, evaluation, and data movement, Vera achieves up to 50% better IPC over its predecessors, offering unprecedented efficiency, throughput, and low-latency performance tailored for complex, concurrent AI environments—positioning it as a true x86 alternative and a cornerstone for upcoming AI systems.

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