HBM Shortages Push AMD To Roll Out Its First Memory On-Package SoC, Meet Versal Gen 2 With 60% Less Board Footprint, 10x Compute & PCIe6 Support

AMD is releasing its first-ever SoCs with an on-package memory solution, the Versal Gen 2, which offers 10x compute uplift.

AMD Versal Gen 2 Ditches HBM For LPDDR5X On-Package Memory, 15-Year Lifecycle & PCIe Gen6 Support

[Editor's Note] The release of Versal Gen 2 marks the first SoC from AMD to feature an on-package memory solution. Compared to Versal Gen 1, the move to LPDDR5X memory comes at a time when the entire tech industry is facing DRAM shortages, and with the prices of HBM products spiraling out of control, AMD is offering LPDDR5X memory on the package itself.

There are up to four LPDDR5X ICs on the Versal Gen 2, offering up to 32 GB capacities and speeds of up to 9000 MT/s, enabling up to 288 GB/s bandwidth. Other key advantages of the MoP design include a 60% reduction in board area, a longer 15-year+ lifecycle, and a 10x compute uplift.

The move to MoP is an interesting one. It is prompted by ongoing shortages, but it might also pave the way for future and more standard SoCs to leverage an on-package solution, which we last saw with Intel's Lunar Lake in the x86 space. Versal is based on the Arm IP, but this design makes an interesting choice for custom-SoC designs to tackle higher memory prices in the next few years.

Press Release: AMD today announced the AMD Versal Premium Gen 2 Memory on Package (MoP) adaptive system-on-chip (SoCs). The MoP architecture integrates up to 32GB of LPDDR5X into a single package, delivering up to 288GB/s of bandwidth in up to 60% less board area, letting engineers build high-bandwidth systems without the risk and time of board-level memory design.

• Integrates up to 32 GB of LPDDR5X on-package to increase memory bandwidth without adding external DRAM
• Delivers up to 288 GB/s of bandwidth to keep AI inference, video processing, and network security workloads moving
• Reduces board area by over 60% versus discrete LPDDR5X designs,1 helping compact systems fit tighter space and thermal envelop.es
• Enables smaller PCIe, PXI, and VPX deployments by moving memory onto the package

Shrink the Footprint and Scale the Bandwidth

With the new memory on a package adaptive SoC, AMD is redefining what is possible in compact system designs. By integrating LPDDR5X directly into the package, the device enables higher performance compared to onboard LPDDR5X while using less area than a discrete offering.

This opens the door to form factors that have been difficult or impractical with external memory, such as the Enterprise and Datacenter Standard Form Factor (EDSFF) and 3U VPX systems, while also helping designers meet telecom and VPX requirements that discrete memory approaches often cannot match.

Versal Premium Gen 2 MoP devices integrate CXL= 3.1 and PCIe 6.0 at 64Gb/s in hard IP, enabling high-speed data movement when paired with AMD EPYC™ CPUs to accelerate data-intensive applications. We help system architects gain greater flexibility to scale memory resources with LPDDR5X support of up to 9,000Mb/s and connectivity to CXL memory pooling and expansion modules.

Device Name	2VP3422	2VP3522	2VP3622
System Logic Cells (K)	2,561	3,273	3,273
CLB LUTs (K)	1,172	1,496	1,496
Total RAM (Mb)*	256	327	327
Integrated LPDDR5X Capacity / Controllers	32 GB / Eight x32b	32 GB / Eight x32b	32 GB / Eight x32b
DSP Engines	6,080	2,512	7,616
PCIe w/ DMA & CXL 3.1 (CPM6)	2x Gen6x8	2x Gen6x8	2x Gen6x8
Max. I/O (XP5IO/MIO)	194 / 78	194 / 78	194 / 78
GTM2 Transceivers	56	72	72

Built for Long Life Cycle Deployments

Designed with demanding physical and enterprise AI environments in mind, Versal Premium Gen 2 MoP adaptive SoCs support industrial-grade operation from -40 degrees Celsius to 110 C. They are well suited for always-on, mission-critical systems where performance and resilience must go hand in hand.

With LPDDR5X and 15-plus-year life cycle support, Versal Premium Gen 2 MoP devices help decouple product availability from high-bandwidth memory (HBM) shorter, data-center-driven refresh cycles, reducing the risk of forced redesigns caused by memory end of life or limited accessibility.

PCIe Integrity and Data Encryption (IDE), a feature introduced in PCIe 6.0, helps protect against physical attacks by securing data in flight at the link layer. DDR memory encryption in integrated controllers helps protect data at rest without consuming programmable logic resources. Hard 400G High-Speed Crypto Engines enable high-bandwidth secure processing, strengthening security without sacrificing throughput.

Accelerate Time-to-Market

Versal Premium Gen 2 MoP devices include a pre-validated, in-package LPDDR5X interface that eliminates high-speed memory routing across the circuit board to reduce board-level simulation and validation while helping shorten development cycles, lower design risk and minimize costly re-spins.

AMD Versal Premium Gen 2 MoP devices begin sampling at the end of 2026, with production shipments expected to begin in the second half of next year. 

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