Details regarding AMD's next-generation EPYC Turin CPUs based on the Zen 5 architecture have been revealed by ExecutableFix & Greymon55. The details talk about the next-gen EPYC TDPs & core counts that we can expect from the first server chips powered by the new Zen architecture.
AMD EPYC Turin Server CPUs Based on Zen Architecture Rumored To Feature Up To 256 Cores & 600W TDPs
The AMD 5th Gen EPYC family, codenamed Turin, will be replacing the Genoa lineup but will be compatible with the SP5 platform. The Turin line of chips could utilize package designs unlike we have ever seen before. The Turin CPUs will be an evolution of the stacked 3D Chiplet designs that we are going to see on EPYC Milan-X CPUs later this year. Considering that Turin will be launching years later, it can be theorized that these EPYC chips will have multiple CCD & Cache stacks on top of the base die.
AMD Genoa CPUs are stated to feature up to 96 cores & Bergamo which is the evolution to Genoa on the same Zen 4 architecture will bring even higher core counts of 128 cores. With Turin, it has been rumored that we could very likely see PCIe Gen 6.0 interface and up to 256 cores on a single chip or even higher if AMD is going for stacked X3D chiplets.
It is stated that the EPYC Turin CPUs will come in two configurations, a 192 core, and 384 thread variant & a 256 core, and 512 thread variant. It will be interesting to see how AMD configures 2x the cores over Bergamo and Genoa on the same SP5 socket. There are two ways AMD could be able to achieve this. The first is to offer twice the number of cores per CCD. Currently, AMD Zen 3 and Zen 4 CCDs feature 8 cores per CCD. With 16 cores per CCD, you can definitely go up to 192 & 256 cores in 12 CCD and 16 CCD configurations.
ZEN5 EPYC should also have two configurations.
— Greymon55 (@greymon55) October 28, 2021
In a previous rumor, MLID had revealed a brand new package layout featuring up to 16 CCDs on the SP5 socket. The second option for AMD which happens to be less likely but also possible would be to stack CCD on top of CCD. AMD could do it for both the 192 and 256 core parts. This will mean that each CCD will retain 8 cores but having two CCDs stacked on top of each other will give 16 cores per CCD-Stack.
As for TDPs, well having double the cores even on a brand new process node (TSMC 3nm) will be pretty hefty for the power budget. It is reported that EPYC Turin will have a max configurable TDP of up to 600W. The upcoming EPYC Genoa CPUs with 96 cores are going to feature cTDPs of up to 400W which while the SP5 socket has a peak power draw of up to 700W. This is very close to that figure.
The AMD EPYC Genoa and SP5 platform leak from Gigabyte already confirmed various info on the next-gen platforms. The LGA 6096 socket will feature 6096 pins arranged in the LGA (Land Grid Array) format. This will be by far the biggest socket that AMD has ever designed with 2002 more pins than the existing LGA 4094 socket. We have already listed the size and dimensions of this socket above so let's talk of its power ratings. It looks like the peak power of the LGA 6096 SP5 socket will be rated at up to 700W which will only last for 1ms, the peak power at 10ms is rated at 440W while the peak power with PCC is rated at 600W. If the cTDP is exceeded, then the EPYC chips featured on the SP5 socket will return to these limits within 30ms.
In addition to this, a leaked AMD slide also confirms future EPYC SOCs to feature higher DDR5 pin speeds of up to 6000-6400 Mbps. This could probably be referring to Turin or Bergamo as they are the ones that succeed Genoa. The EPYC Turin lineup is expected to launch around 2024-2025 & will be pitted against Intel's future Diamond Rapids Xeon platform.
AMD EPYC CPU Families:
|Family Name||AMD EPYC Venice||AMD EPYC Turin||AMD EPYC Siena||AMD EPYC Bergamo||AMD EPYC Genoa-X||AMD EPYC Genoa||AMD EPYC Milan-X||AMD EPYC Milan||AMD EPYC Rome||AMD EPYC Naples|
|Family Branding||EPYC 7007?||EPYC 7006?||EPYC 7004?||EPYC 7005?||EPYC 7004?||EPYC 7004?||EPYC 7003X?||EPYC 7003||EPYC 7002||EPYC 7001|
|CPU Architecture||Zen 6?||Zen 5||Zen 4||Zen 4C||Zen 4 V-Cache||Zen 4||Zen 3||Zen 3||Zen 2||Zen 1|
|Process Node||TBD||3nm TSMC?||5nm TSMC||5nm TSMC||5nm TSMC||5nm TSMC||7nm TSMC||7nm TSMC||7nm TSMC||14nm GloFo|
|Platform Name||TBD||SP5 / SP6||SP6||SP5||SP5||SP5||SP3||SP3||SP3||SP3|
|Socket||TBD||LGA 6096 (SP5)|
LGA XXXX (SP6)
|LGA 4844||LGA 6096||LGA 6096||LGA 6096||LGA 4094||LGA 4094||LGA 4094||LGA 4094|
|Max Core Count||384?||256||64||128||96||96||64||64||64||32|
|Max Thread Count||768?||512||128||256||192||192||128||128||128||64|
|Max L3 Cache||TBD||TBD||256 MB?||TBD||1152 MB?||384 MB?||768 MB?||256 MB||256 MB||64 MB|
|Chiplet Design||TBD||TBD||8 CCD's (1CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD||8 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's (2 CCX's per CCD) + 1 IOD||4 CCD's (2 CCX's per CCD)|
|Memory Channels||TBD||12 Channel (SP5)|
|6-Channel||12 Channel||12 Channel||12 Channel||8 Channel||8 Channel||8 Channel||8 Channel|
|PCIe Gen Support||TBD||TBD||96 Gen 5||160 Gen 5||160 Gen 5||160 Gen 5||128 Gen 4||128 Gen 4||128 Gen 4||64 Gen 3|
|TDP Range||TBD||480W (cTDP 600W)||70-225W||320W (cTDP 400W)||200W (cTDP 400W)||200W (cTDP 400W)||280W||280W||280W||200W|