Aside from the AM5 platform, the leaked Gigabyte documents have also detailed AMD's EPYC Genoa Zen 4 CPUs & SP5 server platform. The data gives us a first look at the next-gen Genoa lineup and architectural improvements brought forward by the 5nm Zen 4 core.
AMD SP5 Platform, EPYC Genoa CPUs & Zen 4 Core Detailed In Gigabyte's Leaked Documents
The AMD EPYC Genoa lineup and the respective SP5 platform that it will feature support on have been in the leaks for quite a while. We know that with EPYC Genoa, AMD will be moving over to a new platform and introducing so many new features that each one deserves a special mention of its own. The Genoa lineup is pinned to ship later this year with a hard launch planned for 2022 as AMD confirmed recently.
Gigabyte's recently leaked document already gave us a detailed look at the AM5 LGA 1718 socket platform and now we are switching gear over to the server segment. The AMD EPYC Genoa CPUs will be based on the Zen 4 core architecture which is fabricated on TSMC's 5nm process node. The leaked documents give us a precise measurement of the Zen 4 die, Genoa package, and SP5 socket which are listed below:
- AMD Zen 4 CCD - 10.70 x 6.75mm (72.225mm2)
- AMD Zen 4 IOD - 24.79 x 16.0mm (396.64mm2)
- AMD EPYC Genoa Substrate (Package) - 72.0 x 75.40mm (5428mm2)
- AMD SP5 LGA 6096 Socket - 76.0 x 80.0mm (6080mm2)
Compared to EPYC Milan, the AMD Zen 4 CCD is 11% smaller than Zen 3 CCD (80mm vs 72mm). The IOD is also 5% smaller (416mm vs 397mm). The package and socket size has increased a lot & that is mainly due to the fact that EPYC Genoa chips incorporate 50% more CCDs than EPYC Milan chips (12 vs 8 CCDs). The Genoa package measures 5428mm2 while the socket has a total area of 6080 mm2 while SP3 measures 4410mm2. Do note how the number of pins comes close to the area size of each respective socket.
The LGA 6096 socket will feature 6096 pins arrange in the LGA (Land Grid Array) format. This will be by far the biggest socket that AMD has ever designed with 2002 more pins than the existing LGA 4094 socket. We have already listed the size and dimensions of this socket above so let's talk of its power ratings. It looks like the peak power of the LGA 6096 SP5 socket will be rated at up to 700W which will only last for 1ms, the peak power at 10ms is rated at 440W while the peak power with PCC is rated at 600W. If the cTDP is exceeded, then the EPYC chips featured on the SP5 socket will return to these limits within 30ms.
AMD EPYC Milan Zen 3 vs EPYC Genoa Zen 4 Size Comparisons:
|CPU Name||AMD EPYC Milan||AMD EPYC Genoa|
|Process Node||TSMC 7nm||TSMC 5nm|
|Core Architecture||Zen 3||Zen 4|
|Zen CCD Die Size||80mm2||72mm2|
|Zen IOD Die Size||416mm2||397mm2|
|Substrate (Package) Area||TBD||5428mm2|
|Socket Name||LGA 4094||LGA 6096|
|Max Socket TDP||450W||700W|
The socket will support AMD's EPYC Genoa and future generations of EPYC chips. Talking about Genoa CPUs themselves, the chips will pack a mammoth 96 cores and 192 threads. These will be based on AMD's brand new Zen 4 core architecture which is expected to deliver some insane IPC uplifts while utilizing the TSMC 5nm process node. A recent rumor had pointed out that the AMD EPYC Genoa CPUs are expected to offer up to 29% IPC uplift over Milan CPUs and a 40% overall improvement thanks to other key technologies that we will get to in a bit.
To get to 96 cores, AMD has to pack more cores in its EPYC Genoa CPU package. AMD is said to achieve this by incorporating a total of up to 12 CCD's in its Genoa chip. Each CCD will feature 8 cores based on the Zen 4 architecture. That aligns with the increased socket size and we could be looking at a massive CPU interposer, even larger than the existing EPYC CPUs. The CPU is said to feature TDPs of 320W which will be configurable up to 400W. This leak also confirms various SKUs that will be part of the Genoa lineup and are listed below:
- 96 Core / 192 Thread - 400W TDP 13 Chiplets (124W IOD Power / 6.7W LGA Power)
- 64 Core / 128 Thread - 400W TDP 9 Chiplets (117W IOD Power / 6.7W LGA Power)
- 96 Core / 192 Thread - 320W TDP 13 Chiplets (124W IOD Power / 5.3W LGA Power)
- 64 Core / 128 Thread - 320W TDP 9 Chiplets (117W IOD Power / 5.3W LGA Power)
- 96 Core / 192 Thread - 300W TDP 13 Chiplets (126W IOD Power / 5W LGA Power)
- 32 Core / 64 Thread - 300W TDP 9 Chiplets (119W IOD Power / 5W LGA Power)
- 96 Core / 192 Thread - 280W TDP 13 Chiplets (126W IOD Power / 4.7W LGA Power)
- 64 Core / 128 Thread - 280W TDP 9 Chiplets (116W IOD Power / 4.7W LGA Power)
- 64 Core / 128 Thread - 260W TDP 9 Chiplets (118W IOD Power / 4.3W LGA Power)
- 32 Core / 64 Thread - 260W TDP 9 Chiplets (118W IOD Power / 4.3W LGA Power)
- 48 Core / 96 Thread - 240W TDP 9 Chiplets (117W IOD Power / 4.0W LGA Power)
- 24 Core / 48 Thread - 240W TDP 5 Chiplets (117W IOD Power / 4.0W LGA Power)
- 48 Core / 96 Thread - 200W TDP 9 Chiplets (117W IOD Power / 3.3W LGA Power)
- 24 Core / 48 Thread - 200W TDP 5 Chiplets (117W IOD Power / 3.3W LGA Power)
- 16 Core / 32 Thread - 195W TDP 5 Chiplets (116W IOD Power / 3.3W LGA Power)
- 8 Core / 16 Thread - 195W TDP 5 Chiplets (116W IOD Power / 3.3W LGA Power)
- 16 Core / 32 Thread - 155W TDP 5 Chiplets (116W IOD Power / 2.6W LGA Power)
- 8 Core / 16 Thread - 155W TDP 5 Chiplets (116W IOD Power / 2.6W LGA Power)
Now that's one area which has seen a massive increase. The current top parts max out at 280W TDPs so a TDP of 400W is an insane 120W more than Milan. But given the increased performance and core counts, we can definitely expect some top-notch efficiency for Genoa. At the same time, we can also expect faster clock speeds, especially the base frequencies which could take a direct benefit of the increased TDP. The IO die will be separate from the CCD's and that will bring up the total chiplet count on the chip to 13.
The mockups above which were made by ExecutableFix are also confirmed as multiple EPYC Genoa die configurations featuring four CCD complexes with 3 CCDs within each complex are shown.
Other than that, it is stated that AMD's EPYC Genoa CPUs will feature 128 PCIe Gen 5.0 lanes of which 112 PCIe Gen 5 lanes will be available since the remaining 16 are reserved, 160 for a 2P (dual-socket) configuration. The SP5 platform will also feature DDR5-5200 memory support which is some insane improvement over the existing DDR4-3200 Mbps DIMMs. But that's not all, it will also support up to 12 DDR5 memory channels and 2 DIMMs per channel which will allow up to 12 TB of system memory using 1 TB 3DS RDIMM modules.
In addition to this, a leaked AMD slide also confirms future EPYC SOCs to feature higher DDR5 pin speeds of up to 6000-6400 Mbps. This could probably be referring to Turin or Bergamo as they are the ones that succeed Genoa.
The main competitor of AMD's EPYC Genoa lineup would be Intel's Sapphire Rapids Xeon family which is expected to launch in 2022 too with PCIe Gen 5 and DDR5 memory support. The lineup was recently rumored to not get a volume ramp until 2023 which you can read more about over here. Overall, AMD's Genoa lineup seems to be in great form after this leak and could be a major disruption for the server segment if AMD plays its cards right till Genoa's launch.
AMD EPYC CPU Families:
|Family Name||AMD EPYC Venice||AMD EPYC Turin||AMD EPYC Siena||AMD EPYC Bergamo||AMD EPYC Genoa-X||AMD EPYC Genoa||AMD EPYC Milan-X||AMD EPYC Milan||AMD EPYC Rome||AMD EPYC Naples|
|Family Branding||EPYC 7007?||EPYC 7006?||EPYC 7004?||EPYC 7005?||EPYC 7004?||EPYC 7004?||EPYC 7003X?||EPYC 7003||EPYC 7002||EPYC 7001|
|CPU Architecture||Zen 6?||Zen 5||Zen 4||Zen 4C||Zen 4 V-Cache||Zen 4||Zen 3||Zen 3||Zen 2||Zen 1|
|Process Node||TBD||3nm TSMC?||5nm TSMC||4nm TSMC||5nm TSMC||5nm TSMC||7nm TSMC||7nm TSMC||7nm TSMC||14nm GloFo|
|Platform Name||TBD||SP5 / SP6||SP6||SP5||SP5||SP5||SP3||SP3||SP3||SP3|
|Socket||TBD||LGA 6096 (SP5)|
LGA XXXX (SP6)
|LGA 4844||LGA 6096||LGA 6096||LGA 6096||LGA 4094||LGA 4094||LGA 4094||LGA 4094|
|Max Core Count||384?||256||64||128||96||96||64||64||64||32|
|Max Thread Count||768?||512||128||256||192||192||128||128||128||64|
|Max L3 Cache||TBD||TBD||256 MB?||TBD||1152 MB?||384 MB?||768 MB?||256 MB||256 MB||64 MB|
|Chiplet Design||TBD||TBD||8 CCD's (1CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD||8 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's (2 CCX's per CCD) + 1 IOD||4 CCD's (2 CCX's per CCD)|
|Memory Channels||TBD||12 Channel (SP5)|
|6-Channel||12 Channel||12 Channel||12 Channel||8 Channel||8 Channel||8 Channel||8 Channel|
|PCIe Gen Support||TBD||TBD||96 Gen 5||160 Gen 5||160 Gen 5||160 Gen 5||128 Gen 4||128 Gen 4||128 Gen 4||64 Gen 3|
|TDP Range||TBD||480W (cTDP 600W)||70-225W||320W (cTDP 400W)||200W (cTDP 400W)||200W (cTDP 400W)||280W||280W||280W||200W|