[UPDATE]AMD Carrizo APU ISSCC 2015 Presentation Leaked – 5% IPC Gain With x86 Excavator, Die Consists of 3.1 Billion Transistors

Hassan Mujtaba
Posted 2 years ago

Update: Since it’s just about time that when AMD presents Carrizo APU at ISSCC 2015, we wanted to give some additional details on the Carrizo APU which can be found below in the article. In case you are unable to find the mentioned details, you can browse at the very end of the article to find first benchmarks of AMD Carrizo APUs in 3DMark along with more detailed information on the die size of the new chip.

AMD’s Carrizo APU presentation to be displayed during the upcoming ISSCC 2015 event has been leaked ahead of its time by Videocardz. The slides show all of what we have expected from Carrizo to be a mobility core that features the latest x86 Excavator core architecture and GCN graphics architecture, combining them to deliver a full SOC design for mobility platforms.

Image Credits: Videocardz

AMD Carrizo APU Detailed – IPC Gains, Power Efficiency, Low-Power States Explained

To start off this article, there’s a few things we need to recap first. AMD’s Carrizo APU was displayed first by John Byrne (Former SVP and GM of AMD Computing & Graphics Business Unit) in late 2014. Since the launch, AMD has undergone several structural changes including John leaving the company while Lisa Su talking chair as the CEO of the company. The first shock came when it was reported that Carrizo and Carrizo-L won’t be a feature product for the desktop platform and will be limited to mobility platforms only. The company will now instead focus on a refresh based on current Kaveri APUs codenamed “Godavari” to satisfy consumers until they launch their Excavator powered “Bristol Ridge” APUs in 2016. It might also suggest that Carrizo’s successor will be updated from the architecture side while desktop platforms will stay one step back with the current high-performance x86 node (Excavator).

Coming to the architecture of the APU itself, it was expected that like Kaveri before it, Carrizo won’t be a revolutionary chip. It is based on the current iteration of GCN architecture and the Excavator core itself is a more enhanced and derived form of the construction cores which started with Bulldozer in 2012. So we are looking at a nominal 5% IPC gains from the new Excavator cores which shows AMD is following Intel footsteps in this field with the blue team also offering a similar IPC improvement on their latest 14nm Broadwell Uarch. The die is still based on a 28nm node yet AMD has managed to optimize the overall chip design by adding 29% more transistors than Kaveri thanks to the high-density design library. This results in a 3.1 Billion transistor die that delivers 40% lesser power consumption and 23% lesser die area than its predecessor. The H.265 encode support allows 3.5 times transcode performance of Kaveri while the compute architecture enables the 8 GCN compute units (512 stream processors) a reduction of 20% in power consumption. AMD talks of a double digit increase in both the performance and battery sector however they are no where near the gains we expected earlier from Carrizo.

In terms of size, the Carrizo die measures at 244.62mm2 on the 28nm node while Kaveri measures at 245mm2 on the same process. The difference between both chips is that Carrizo ups the transistor count to 3.1 billion from Kaveri’s 2.41 billion count. The sudden reduction in the size of the die even when adding more better x86 performance was due to the fact that Excavator cores are smaller than Steamroller cores, measuring at just 14.48mm2 with a core transistor count of 102 million transistors. The L1 cache has also doubled on Carrizo to 32 KB per core from 16 KB. The overall core structure has 690 million transistors crammed in one partition while the rest of the transistors are dedicated to GCN cores that utilize HSA and compute engine advantage in general purpose computing environments.

AMD Bristol Ridge Processors For Mobility (FP4) Launched - Fine Tuned Carrizo With Better IPC and Faster GCN Cores, Designed For Laptops

AMD Carrizo APU Power Optimization Features

AMD Carrizo APU_Excavator Core Architecture

We will get back to the technical bits in a moment after detailing the power optimization features. Based on the Excavator architecture, the Carrizo APUs are more denser with each cell being 35% smaller than Kaveri e.g. FPS/FMAC/I-Cache. AMD has also managed to create a more general purpose GPU-Oriented stack that helps achieve this new FIN stacking implementation compared to prior generation designs. On the graphics front, AMD achieves 18% leakage reduction and gate-timing with faster RVT devices that enables 10% higher frequency while consuming sipping the same level of power.


So an 8 CU GCN module that previously shipped around 28W will be down to just 22W with Carrizo. AMD has implemented several AVFS modules inside the Excavator core that extract the true silicon speed capability of the core by balancing between the voltage, temperatures and available headroom. This provides an additional power reduction level over the High-density library gains. Lastly, AMD has introduced a new low power state on Carrizo called S0i3 which is also known as the Standby state that leaves just the ACP and FCH running and keeps everything else off to allow the chip to operate at just 50mW, conserving battery life. In idle state, the CPU, GPU and most of the PLL blocks would be disabled to result in a 1.5W power consumption. Voltage adaptive operations further lead to a 19% (CPU) and 10% (GPU) power savings.

AMD Carrizo APU Features – What’s Under The Hood?

AMD Carrizo APU_28nm x86 5 IPC

We have already detailed previously about the features that Carrizo will pack underneath its die. Some features presented in the slides mention a single, scalable infrastructure that will be shared with Carrizo-L since we have known that both chips are pin-to-pin compatible. They come with GCN graphics supporting Mantle, DirectX 12 and Dual graphics. Both the single-chip integration of the APU and the southbridge are located on a single die and HSA 1.0 is fully implemented that also helps improve energy efficiency. AMD will also add AVX2, BMI2, MOVBE and RDRAND support to the instruction set which brings the extension feature set close to Intel’s Haswell. Since the targeted platforms for these APUs are notebooks, all-in-ones and convertibles, they will be shipped in BGA )FP4) package and will ship in variants ranging in TDPs of 12/15/35W.

The most interesting thing about Carrizo, aside from its technical specifications is also the design of the chip itself. AMD for the first time is aiming for a true SOC design eliminating the need of a separate FCH as was the case with Kaveri mobile which requires Bolton FCH for additional connectivity options. The FCH will be integrated on the die itself which will deliver Security, Display, Audio, PCI-e, SATA, SD, USB, Multimedia, UART/12C. CLCKGen and Misc I/O connectivity. AMD is aiming for UVD6, VCE3 and a audio co-processors with H.264 encode while feature a display control engine “DCE11″. With HDMI 2.0 that provides up to 3 display interfaces and PCI-e Gen 3.0 x8 for discrete GPU expansion and PCI-e 3.0 x4 for GPP, the APU begins to look like a decent improvement over Kaveri from a design perspective.  The FCH can deliver 4 USB 3.0 / 2.0 ports, 4 USB 2.0 ports and 2 SATA 3 ports while the memory controller allow for Dual Channel DDR3 memory rated at 2133 MHz in SoDIMM form factor (One per channel).

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AMD FX-8800P Could Be Flagship Carrizo Mobile APU – 3DMark Benchmark Revealed

The listing of an AMD FX-8800P came all of a sudden when AMD is still a few months away from launching their Carrizo mobile APU. The last flagship APU that was part of AMD’s Kaveri family was codenamed FX-7600P and the FX-8800P seems to be its successor from the Carrizo APU family. The 3DMark benchmark is vague on specs and details but it does list the FX-8800P as a 12 Compute Cores enabled part which confirms that the Carrizo APU on mobility will feature a maximum of 4 x86 Excavator cores and 8 GCN Compute units forming into the 12 Compute Cores which AMD has been branding since the launch of Kaveri (because the can be used as GPGPU). The testing was performed on the AMD Gardenia platform which is an internal codename for the test board that is used to run Carrizo samples. Rest of the specifications include the Radeon R7 graphics branding for the 512 SPs iGPU and a preliminary clock speed of 1.7 GHz base and 2.1 GHz boost. The chip scores around 2645 points in 3DMark 11 performance mode which can be compared to the 2150 (average performance) score of the Kaveri based FX-7600P APU.

AMD Carrizo is expected to hit the mobility market in mid of 2015 and the AMD presentation at ISSCC 2015 commences on 23rd February (4:45 PM Pacific US Time) so more details are expected but nothing that we know already.

AMD Carrizo APU ISSCC 2015 Slides (Courtesy of Videocardz)

AMD x86 Excavator Core Block Diagram:

Excavator Core Block Diagram

AMD Carrizo APU Official Presentation Slides:

AMD Carrizo APU Slide

AMD Carrizo APU Roadmap

AMD Carrizo APU Comparison Chart:

  AMD Trinity APU AMD Richland APU AMD Kaveri APU AMD Carrizo-L AMD Carrizo APU
Core x86 Piledriver x86 Piledriver x86 Steamroller x86 PUMA+ x86 Excavator
Cores 2-4 2-4 2-4 2-4 2-4
GPU HD 7000
HD 8000
2nd GCN
Sea Islands
2nd GCN
Sea Islands
3rd GCN
Volcanic Islands
GCN Cores 384 SPs 384 SPs 512 SPs 128 SPs? 512 SPs
Chipset A85X/A75/FCH A88X/A78/FCH A88X/A78/Bolton SOC SOC
TDP 17/25/35W 17/25/35W 17/19/35W 10/25W 15-35W
HSA Support  No No Yes Yes Full HSA 1.0

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