The IEEE ISSCC 2026 conference will be hosted in February 2026, with lots of papers to be presented, including GDDR7, HBM4 & LPDDR6.
Talks On Several Chips, Interconnect Solutions & DRAM Products Including GDDR7, HBM4, LPDDR6, To Be Presented At ISSCC 2026
The IEEE Solid-State Circuits conference is all set to be presented in February 2026 in San Francisco. The conference will last five days and will host various talks, including research papers on existing and next-generation technologies. Just for reference, the following is the list of paper sessions segments that will be presented at ISSCC 2026:
- Processors
- Wearable and Wireless Biomedical Systems
- Analog Techniques & Amplifiers
- Sub-THz and mm-Wave Phased Arrays and Beamformers
- Exploratory Receiver Architectures from GHz to THz
- Image Sensors and Ranging
- Die-to-Die and High-Speed Electrical Transceivers
- Wireless Power
- Digital Processing and Circuit Techniques
- Pipeline and Ultra-High-Speed Data Converters
- Frequency Synthesizers and VCOs
- Circuits for AI and AI for Circuits
- Unusual Interconnects and Other Uses for Light
- DRAM, SRAM, and Non-Volatile Memories
- Energy Harvesting, Piezo, and Chargers
- Highlighted Chip Releases for AI
- Technology and Circuits for Domain-Specific Accelerators
- High-Voltage, Isolated, and Display Power
- RF Transceiver Subsystems from cm-Wave to THz
- Sensor Interfaces
- Circuits in Extreme Environments
- Next-Generation Optical Transceivers
- Displays
- Hardware Security
- Compute Power and Supply Modulators
- Frequency Generators, Multipliers, and Modulators
- Innovations from Outside the (ISSCC) Box
- Biochemical Sensors for Life Sciences and Agriculture
- Compute-in-Memory
- AI Accelerators
- Low-Power Noise-Shaping ADCs
- Time-Varying Circuit Techniques from RF to mm-Wave
- Integrated Radar and UWB Transceivers from Microwave to Sub-THz
- Low Power Wireless Transceivers for Localization and Communications
- Neural and Biomedical Interfaces
- Memory Interface
As you can tell, the list is quite extensive, and each segment has several research papers from various firms, companies, and Universities.
Among the list are a few highlights, such as the DRAM segment, which talks about GDDR7 DRAM, HBM4 DRAM, and LPDDR6 DRAM.
Starting with GDDR7 DRAM, SK hynix will present a new paper in which it will talk about its 48 Gbps G7 solution featuring 24 Gb densities. 24 Gb equals 3 GB of memory capacity, and the company is utilizing symmetric 2-channel mode operation with clock-path optimization and RAS features. It should be noted that SK hynix has laid out its GDDR7 plans up to 40 Gbps and up to 24 Gb densities, so this is a big boost in speeds.
48 Gbps speeds will bring over 70% improvement in transfer rates with a single DRAM producing up to 192 GB/s of bandwidth versus 112 GB/s bandwidth produced with current 28 Gbps dies.
It is unlikely that we will see GDDR7 speeds of such a level anytime soon, maybe future GPUs such as RTX 40 Refresh might be able to get us near 48 Gbps. The same was the case with GDDR6, which was expected to feature speeds as high as 24 Gbps with Samsung's GDDR6W solution, but that hasn't been the case so far.
In addition to GDDR7, SK hynix will also present its research paper on 1cnm LPDDR6 SDRAM with up to 14.4 Gbps pin speeds and 16 Gb density. Similarly, Samsung will be presenting its own LPDDR6 research paper, which has rated speeds of 12.8 Gbps and 16 Gb densities. Lastly, we will see Samsung present its HBM4 DRAM research paper, which features 36 GB of HBM capacity using a 12-Hi solution and offers up to 3.3 TB/s of bandwidth per stack. Samsung is in line to offer its HBM4 solution for NVIDIA's upcoming Vera Rubin AI Accelerators.
GDDR Graphics Memory Evolution:
| GRAPHICS MEMORY | GDDR7 | GDDR6X | GDDR6 | GDDR5X |
|---|---|---|---|---|
| Workload | Gaming / AI | Gaming / AI | Gaming / AI | Gaming |
| Platform (Example) | GeForce RTX 5090 | GeForce RTX 4090 | GeForce RTX 2080 Ti | GeForce GTX 1080 Ti |
| Die Capacity (Gb) | 16-64 | 8-32 | 8-32 | 8-16 |
| Number of Placements | 12 | 12 | 12 | 12 |
| Gb/s/pin | 28-48 | 19-24 | 14-16 | 11.4 |
| GB/s/placement | 112-192 | 76-96 | 56-64 | 45 |
| GB/s/system | 1536-2304 | 912-1152 | 672-768 | 547 |
| Configuration (Example) | 384 IO (12pcs x 32 IO package)? | 384 IO (12pcs x 32 IO package) | 384 IO (12pcs x 32 IO package) | 384 IO (12pcs x 32 IO package) |
| Frame Buffer of Typical System | 24 GB (16 Gb) 36 GB (24 Gb) | 24 GB | 12GB | 12GB |
| Module Package | 266 (BGA) | 180 (BGA) | 180 (BGA) | 190 (BGA) |
| Average Device Power (pJ/bit) | TBD | 7.25 | 7.5 | 8.0 |
| Typical IO Channel | PCB (P2P SM) | PCB (P2P SM) | PCB (P2P SM) | PCB (P2P SM) |
These are just some of the many interesting topics that will be presented during ISSCC 26. Intel, NVIDIA, and AMD also have several research papers lined up, so expect technical and in-depth sessions from the conference.
News Source: Ruby_Rapids
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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