Intel Confirms Cooper Lake-SP 14nm Xeon CPUs in 2019, Ice Lake-SP 10nm CPUs in 2020 – More Details on Cascade Lake-SP Xeon CPUs Revealed
Intel has just unveiled their latest Xeon Scalable Family roadmap which includes next-generation 14nm and 10nm processors for HPC and Datacenters. The roadmap confirms what we have been hearing regarding Intel's Xeon platform since a while now so let's have a look at what Intel has to offer in the coming years.
Intel Xeon Scalable Family Next-Gen Platforms Confirms - Cooper Lake-SP 14nm Xeons in 2019, Ice Lake-SP 10nm Xeons in 2020
During their Data-Centric Innovation Summit, Intel announced a new roadmap which confirmed their upcoming Xeon platforms. We have known about Cascade Lake-SP since a while now but now, we know what Intel is prepping for the future. Intel also revealed new details about Cascade Lake-SP Xeons which were not known before.
- Cascade Lake is a future Intel Xeon Scalable processor based on 14nm technology that will introduce Intel Optane DC persistent memory and a set of new AI features called Intel DL Boost. This embedded AI accelerator will speed deep learning inference workloads, with an expected 11 times faster image recognition than the current generation Intel Xeon Scalable processors when they launched in July 2017. Cascade Lake is targeted to begin shipping late this year.
- Cooper Lake is a future Intel Xeon Scalable processor that is based on 14nm technology. Cooper Lake will introduce a new generation platform with significant performance improvements, new I/O features, new Intel® DL Boost capabilities (Bfloat16) that improve AI/deep learning training performance, and additional Intel Optane DC persistent memory innovations. Cooper Lake is targeted for 2019 shipments.
- Ice Lake is a future Intel Xeon Scalable processor based on 10nm technology that shares a common platform with Cooper Lake and is planned as a fast follow-on targeted for 2020 shipments.
The details show that Intel is currently planning the Cascade Lake-SP family for launch later this year. The processors are expected to start shipping to customers in Q4 2018. The new chips will utilize the 14nm+ node, featuring higher efficiency and retain support on the existing Purley platform while offering new feature and I/O expandability. There will also be support for Intel's Optane Persistent memory, Intel Deep Learning Boost (VNNI) and security mitigations against Spectre and Meltdown threats.
The launch will take place at the end of Q4 2018 for top-tier customers which are focused towards hyper-scale compute while general availability is expected in Q1 2019. The new Deep Learning boost algorithm would help boost inferencing performance by 11x over the previous generation of Scalable processors (Syklake-SP). Intel did a small demo, showcasing a next-generation Cascade Lake-SP processor against Skylake-SP in Resnet-50 which showed the mentioned performance gains.
Intel Cooper Lake-SP 14nm and Ice Lake-SP 10nm Xeons Are Designed For Next-Gen ‘Whitley’ Platform
Next up, we have the Whitely platform which will feature two Xeon Scalable Families. First one is the Cooper Lake-SP family which will be introduced at the end of 2019. The Cooper Lake CPUs will retain the 14nm process node and feature small efficiency enhancements but will be supported by a completely new platform known as Whitley which is the successor to Purley. Cooper-Lake Xeons would also deliver an updated to Intel's Deep Learning Boost by offering support for BFLOAT 16 instructions.
Later in mid of 2020, Intel would introduce their first 10nm Scalable processor family, the Ice Lake-SP. While it was first expected to launch earlier, the 10nm product woes had resulted in a really bad situation for the entire Intel CPU family which has resulted in several delays and various product cancellations.
While Intel didn't mention much about their Ice Lake-SP processors aside from saying they'll be based on a 10nm process, we know from previous details that the Ice Lake-SP Xeon family will be supported by the same Whitley platform and come with an enhanced CPU/IO architecture layout. We can expect a core count bump and processors will retain support for 2S / 4S / 8S+ platforms.
While the current Skylake-SP Xeon family uses the LGA 3647 socket and housed on the Purely platform which will exist up till Cascade Lake-SP Xeon parts, the Ice Lake-SP family will use an entirely new socket design. This is termed as the LGA 4189 socket and will be Intel’s largest pin socket design to date. The socket will be even larger than the AMD’s TR4 / SP4 socket for Ryzen Threadripper and EPYC part which comes with 4094 LGA pins.
Coming to CPU support, the post Purely platform will house up to 230W CPUs. Note that current Skylake-SP Xeons range from 140W to 205W variants while Cascade Lake-SP parts scale from 165 to 205W variants. The higher TDP would be due to several reasons, we can see a core count and clock speed bump in addition to the expected implementation of OmniPath and on-package FPGAs features which would make a whole lot of sense for high-end Xeon Ice Lake-SP parts.
Whitley would feature a total of 16 slots dedicated to each CPU which points out to having an octa-channel memory support. This is higher than the hexa-channel memory that we are aware of on the Skylake-SP part. The Cascade Lake-SP platform features support for 2933 MHz DDR4 memory. The extra memory slots can bump the memory all the way up to 1 TB (per socket) from the current maximum of 786 GB using the highest density products.
Intel Xeon SP Families:
|Family Branding||Skylake-SP||Cascade Lake-SP/AP||Cooper Lake-SP||Ice Lake-SP||Sapphire Rapids||Emerald Rapids||Granite Rapids||Diamond Rapids|
|Process Node||14nm+||14nm++||14nm++||10nm+||10nm Enhanced SuperFin?||10nm Enhanced SuperFin?||7nm?||sub-7nm?|
|Platform Name||Intel Purley||Intel Purley||Intel Cedar Island||Intel Whitley||Intel Eagle Stream||Intel Eagle Stream||Intel Mountain Stream|
Intel Birch Stream
|Intel Mountain Stream
Intel Birch Stream
|MCP (Multi-Chip Package) SKUs||No||Yes||No||No||Yes||TBD||TBD (Possibly Yes)||TBD (Possibly Yes)|
|Socket||LGA 3647||LGA 3647||LGA 4189||LGA 4189||LGA 4677||LGA 4677||LGA 4677||TBD|
|Max Core Count||Up To 28||Up To 28||Up To 28||Up To 40||Up To 56?||TBD||TBD||TBD|
|Max Thread Count||Up To 56||Up To 56||Up To 56||Up To 80||Up To 112?||TBD||TBD||TBD|
|Max L3 Cache||38.5 MB L3||38.5 MB L3||38.5 MB L3||60 MB L3||TBD||TBD||TBD||TBD|
|Memory Support||DDR4-2666 6-Channel||DDR4-2933 6-Channel||Up To 6-Channel DDR4-3200||Up To 8-Channel DDR4-3200||Up To 8-Channel DDR5-4800||Up To 8-Channel DDR5-5200?||TBD||TBD|
|PCIe Gen Support||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 4.0 (64 Lanes)||PCIe 5.0 (80 lanes)||PCIe 5.0||PCIe 6.0?||PCIe 6.0?|
|TDP Range||140W-205W||165W-205W||150W-250W||105-270W||Up To 350W?||TBD||TBD||TBD|
|3D Xpoint Optane DIMM||N/A||Apache Pass||Barlow Pass||Barlow Pass||Crow Pass||Crow Pass?||Donahue Pass?||Donahue Pass?|
|Competition||AMD EPYC Naples 14nm||AMD EPYC Rome 7nm||AMD EPYC Rome 7nm||AMD EPYC Milan 7nm+||AMD EPYC Genoa ~5nm||AMD Next-Gen EPYC (Post Genoa)||AMD Next-Gen EPYC (Post Genoa)||AMD Next-Gen EPYC (Post Genoa)|
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