Intel Xeon Scalable Family Roadmap Revealed – Points Out 14nm Cascade Lake-SP in Q4 2018, Cooper Lake-SP in Q4 2019, 10nm Ice Lake-SP in 1H 2020
The latest Intel Xeon Scalable family roadmap has leaked out, revealing several Xeon products that are planned to launch in the coming years. We know that Intel is launching their Cascade Lake-SP processors this year but the roadmap points out to future Xeon families up till 2020, as pointed out by the roadmap.
Intel Xeon Scalable Family Roadmap Reveals 14nm Cooper Lake-SP in 2019, 10nm Ice Lake-SP in 2020 and Next-Generation Xeon Post-2020
The details show that Intel is currently planning the Cascade Lake-SP family for launch later this year. Based on the 14nm+ node, the Cascade Lake-SP Xeons would feature higher efficiency and retain support on the existing Purley platform, while offering new feature and I/O expandability. The following lineups are expected under the Cascade Lake family:
- Intel Cascade Lake-AP “Advanced Processor Family” (BGA 5903)
- Intel Cascade Lake-SP “Scalable Processor Family” (LGA 3647)
- Intel Cascade Lake-X “HEDT Consumer Family” (LGA 3647)
Now, we have known Cascade Lake-SP family for a while and the Cascade Lake-X family will have lots of similarities with it. Both Cascade Lake-SP and Cascade Lake-X processors will be featuring support for the LGA 3647 socket. Both families will have support for 6 channel memory and we can also expect faster memory support of DDR4-2800 (native). Cascade Lake-SP processors will be the first to feature Optane DIMM support which is shipping later this year but this cannot be said to be true for Cascade Lake-X series. The Cascade Lake Xeons would feature up to 28 cores and 56 threads, the same configurations would be made available to enthusiasts in the form of Cascade Lake-X.
Moving on to the Cascade Lake-AP series, the new family will be the first to use the “Advanced Processor” badge. Expected to hit markets in the mid of 2019 and under the 'Walker Pass' brand platform, the Cascade Lake Advanced Processor lineup is Intel trying to regain their momentum on the server side after taking a huge hit by AMD’s disruptive EPYC line of CPUs that offer more cores, more memory, and more PCIe lanes while retaining Intel’s level of IPC. This has taken a toll on Intel’s market share and the effects are apparent with Intel’s CEO, Brian Krzanich, expecting his company to lose server market share to AMD’s new platform.
The advanced processor lineup will be something that can put Intel back in the lead with disruptive core count and higher I/O capabilities. Just how would Intel achieve that with a new line of CPUs? The answer is MCM. Intel for the moment relies on monolithic dies and they have had multiple slides showcasing the benefits of such solutions, however, monolithic dies are expensive and have several constraints which are starting to show their effect on Intel CPUs. AMD is taking the lead in multiple areas and both EPYC and Threadripper have put them in a visible lead against the blue team chips.
With Cascade Lake-AP, Intel plans to execute their own MCM (Multi-Chip-Module) approach. An industry insider, Ashraf Essa, has previously heard rumors of the Advanced Processor lineup and mentioned that it wasn’t expected until the Ice Lake generation. But now with the EPYC series proving to be crushing Intel in one of their dominant markets, there’s no doubt that they’ll end up using an MCM approach a generation early. You can learn more about the Advanced Processors over here.
Intel Xeon SP Families:
|Family Branding||Skylake-SP||Cascade Lake-SP/AP||Cooper Lake-SP||Ice Lake-SP||Sapphire Rapids||Emerald Rapids||Granite Rapids||Diamond Rapids|
|Process Node||14nm+||14nm++||14nm++||10nm+||10nm Enhanced SuperFin?||10nm Enhanced SuperFin?||7nm?||sub-7nm?|
|Platform Name||Intel Purley||Intel Purley||Intel Cedar Island||Intel Whitley||Intel Eagle Stream||Intel Eagle Stream||Intel Mountain Stream|
Intel Birch Stream
|Intel Mountain Stream
Intel Birch Stream
|MCP (Multi-Chip Package) SKUs||No||Yes||No||No||Yes||TBD||TBD (Possibly Yes)||TBD (Possibly Yes)|
|Socket||LGA 3647||LGA 3647||LGA 4189||LGA 4189||LGA 4677||LGA 4677||LGA 4677||TBD|
|Max Core Count||Up To 28||Up To 28||Up To 28||Up To 40||Up To 56?||TBD||TBD||TBD|
|Max Thread Count||Up To 56||Up To 56||Up To 56||Up To 80||Up To 112?||TBD||TBD||TBD|
|Max L3 Cache||38.5 MB L3||38.5 MB L3||38.5 MB L3||60 MB L3||TBD||TBD||TBD||TBD|
|Memory Support||DDR4-2666 6-Channel||DDR4-2933 6-Channel||Up To 6-Channel DDR4-3200||Up To 8-Channel DDR4-3200||Up To 8-Channel DDR5-4800||Up To 8-Channel DDR5-5200?||TBD||TBD|
|PCIe Gen Support||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 4.0 (64 Lanes)||PCIe 5.0 (80 lanes)||PCIe 5.0||PCIe 6.0?||PCIe 6.0?|
|TDP Range||140W-205W||165W-205W||150W-250W||105-270W||Up To 350W?||TBD||TBD||TBD|
|3D Xpoint Optane DIMM||N/A||Apache Pass||Barlow Pass||Barlow Pass||Crow Pass||Crow Pass?||Donahue Pass?||Donahue Pass?|
|Competition||AMD EPYC Naples 14nm||AMD EPYC Rome 7nm||AMD EPYC Rome 7nm||AMD EPYC Milan 7nm+||AMD EPYC Genoa ~5nm||AMD Next-Gen EPYC (Post Genoa)||AMD Next-Gen EPYC (Post Genoa)||AMD Next-Gen EPYC (Post Genoa)|
Intel Cooper Lake-SP 14nm and Ice Lake-SP 10nm Xeons Are Designed For Next-Gen 'Whitley' Platform
Next up, we have the Whitely platform which will feature two Xeon Scalable Families. First one is the Cooper Lake-SP family which will be introduced at the end of 2019. The Cooper Lake CPUs will retain the 14nm process node and feature small efficiency enhancements but will be supported by a completely new platform known as Whitley which is the successor to Purley.
Later in mid of 2020, Intel would introduce their first 10nm Scalable processor family, the Ice Lake-SP. While it was first expected to launch earlier, the 10nm product woes had resulted in a really bad situation for the entire Intel CPU family which has resulted in several delays and various product cancellations.
This family will be supported by the same Whitley platform and come with an enhanced CPU/IO architecture layout. We can expect a core count bump and processors will retain support for 2S / 4S / 8S+ platforms.
While the current Skylake-SP Xeon family uses the LGA 3647 socket and housed on the Purely platform which will exist up till Cascade Lake-SP Xeon parts, the Ice Lake-SP family will use an entirely new socket design. This is termed as the LGA 4189 socket and will be Intel’s largest pin socket design to date. The socket will be even larger than the AMD’s TR4 / SP4 socket for Ryzen Threadripper and EPYC part which comes with 4094 LGA pins.
Coming to CPU support, the post Purely platform will house up to 230W CPUs. Note that current Skylake-SP Xeons range from 140W to 205W variants while Cascade Lake-SP parts scale from 165 to 205W variants. The higher TDP would be due to several reasons, we can see a core count and clock speed bump in addition to the expected implementation of OmniPath and on-package FPGAs features which would make a whole lot of sense for high-end Xeon Ice Lake-SP parts.
Whitley would feature a total of 16 slots dedicated to each CPU which points out to having an octa-channel memory support. This is higher than the hexa-channel memory that we are aware of on the Skylake-SP part. The Cascade Lake-SP platform features support for 2933 MHz DDR4 memory. The extra memory slots can bump the memory all the way up to 1 TB (per socket) from the current maximum of 786 GB using the highest density products.
There's also a mention of a next-generation AP part with a 'TBD Pass' label attached to it. There are no details but these HPC focused chips will launch sometime in mid of 2020. A next-generation SP Xeon family is also listed for Post-2020 aiming the Tinsley platform which will be coupled with new Sapphire Rapids core architecture but that is still a couple of years away. This roadmap shows only a glimpse of what Intel has to offer in the Xeon (workstation/datacenter/HPC) segment. It will be a really crucial few years for the company with the resurgence of AMD and their EPYC line of CPUs as having already hinted to compete favorably against their Ice Lake-SP (2020) chips a year earlier and on a much smaller 7nm node.
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