The Biggest Server CPU Package To Date: AMD's EPYC Genoa Powered By Zen 4, For SP5 Socket, Shows Itself Off In Leaked Pictures
The AMD EPYC Genoa CPUs are going to be a powerful computing platform for the HPC and data center segment but they are also monstrous in terms of sheer proportions. The leaked image has revealed the entire physical package of the Genoa chip and it looks like AMD already has a few of those Zen 4 prototypes running at its labs as seen in the leaked image. There's no way to confirm the model or OPN since that has been blurred out by the leaker but this is definitely a real chip & it comes with an SP5 carrier frame around it for easier installation within the massive LGA 6960 CPU socket.
AMD EPYC Genoa CPUs - 5nm Zen 4 & Up To 96 Cores In 2022
Starting with the details, AMD has already announced that EPYC Genoa would be compatible with the new SP5 platform which brings a new socket so SP3 compatibility would exist up till EPYC Milan. The EPYC Genoa processors would also feature support for new memory and new capabilities. In the latest details, it is reported that the SP5 platform will also feature a brand new socket that will feature 6096 pins arranged in the LGA (Land Grid Array) format. This will be by far the biggest socket that AMD has ever designed with 2002 more pins than the existing LGA 4094 socket.
AMD EPYC Milan Zen 3 vs EPYC Genoa Zen 4 Size Comparisons:
|CPU Name||AMD EPYC Milan||AMD EPYC Genoa|
|Process Node||TSMC 7nm||TSMC 5nm|
|Core Architecture||Zen 3||Zen 4|
|Zen CCD Die Size||80mm2||72mm2|
|Zen IOD Die Size||416mm2||397mm2|
|Substrate (Package) Area||TBD||5428mm2|
|Socket Name||LGA 4094||LGA 6096|
|Max Socket TDP||450W||700W|
The socket will support AMD's EPYC Genoa and future generations of EPYC chips. Talking about Genoa CPUs themselves, the chips will pack a mammoth 96 cores and 192 threads. These will be based on AMD's brand new Zen 4 core architecture which is expected to deliver some insane IPC uplifts while utilizing the TSMC 5nm process node.
To get to 96 cores, AMD has to pack more cores in its EPYC Genoa CPU package. AMD is said to achieve this by incorporating a total of up to 12 CCD's in its Genoa chip. Each CCD will feature 8 cores based on the Zen 4 architecture. That aligns with the increased socket size and we could be looking at a massive CPU interposer, even larger than the existing EPYC CPUs. The CPU is said to feature TDPs of 320W which will be configurable up to 400W. You can find more details regarding the SP5 platform here.
Other than that, it is stated that AMD's EPYC Genoa CPUs will feature 128 PCIe Gen 5.0 lanes, 160 for a 2P (dual-socket) configuration. The SP5 platform will also feature DDR5-5200 memory support which is some insane improvement over the existing DDR4-3200 MHz DIMMs. But that's not all, it will also support up to 12 DDR5 memory channels and 2 DIMMs per channel which will allow up to 3 TB of system memory using 128 GB modules.
The main competitor of AMD's EPYC Genoa lineup would be Intel's Sapphire Rapids Xeon family which is expected to launch in 2022 too with PCIe Gen 5 and DDR5 memory support. The lineup was recently rumored to not get a volume ramp until 2023 which you can read more about over here. Overall, AMD's Genoa lineup seems to be in great form after this leak and could be a major disruption for the server segment if AMD plays its cards right till Genoa's launch by 2022.
AMD EPYC CPU Families:
|Family Name||AMD EPYC Venice||AMD EPYC Turin||AMD EPYC Siena||AMD EPYC Bergamo||AMD EPYC Genoa-X||AMD EPYC Genoa||AMD EPYC Milan-X||AMD EPYC Milan||AMD EPYC Rome||AMD EPYC Naples|
|Family Branding||EPYC 7007?||EPYC 7006?||EPYC 7004?||EPYC 7005?||EPYC 7004?||EPYC 7004?||EPYC 7003X?||EPYC 7003||EPYC 7002||EPYC 7001|
|CPU Architecture||Zen 6?||Zen 5||Zen 4||Zen 4C||Zen 4 V-Cache||Zen 4||Zen 3||Zen 3||Zen 2||Zen 1|
|Process Node||TBD||3nm TSMC?||5nm TSMC||4nm TSMC||5nm TSMC||5nm TSMC||7nm TSMC||7nm TSMC||7nm TSMC||14nm GloFo|
|Platform Name||TBD||SP5 / SP6||SP6||SP5||SP5||SP5||SP3||SP3||SP3||SP3|
|Socket||TBD||LGA 6096 (SP5)|
LGA XXXX (SP6)
|LGA 4844||LGA 6096||LGA 6096||LGA 6096||LGA 4094||LGA 4094||LGA 4094||LGA 4094|
|Max Core Count||384?||256||64||128||96||96||64||64||64||32|
|Max Thread Count||768?||512||128||256||192||192||128||128||128||64|
|Max L3 Cache||TBD||TBD||256 MB?||TBD||1152 MB?||384 MB?||768 MB?||256 MB||256 MB||64 MB|
|Chiplet Design||TBD||TBD||8 CCD's (1CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD||8 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's (2 CCX's per CCD) + 1 IOD||4 CCD's (2 CCX's per CCD)|
|Memory Channels||TBD||12 Channel (SP5)|
|6-Channel||12 Channel||12 Channel||12 Channel||8 Channel||8 Channel||8 Channel||8 Channel|
|PCIe Gen Support||TBD||TBD||96 Gen 5||160 Gen 5||160 Gen 5||160 Gen 5||128 Gen 4||128 Gen 4||128 Gen 4||64 Gen 3|
|TDP Range||TBD||480W (cTDP 600W)||70-225W||320W (cTDP 400W)||200W (cTDP 400W)||200W (cTDP 400W)||280W||280W||280W||200W|