AMD Announces High Bandwidth Memory – Innovative Vertically Stacked Memory Standard
Last year SK Hynix, the memory manufacturer that co-developed HBM with AMD had published its first comprehensive public documentation of the revolutionary memory technology. We published an article last year in which we discussed the new memory technology in-depth and its implications in the industry as a whole.
The presentation released by SK Hynix last year detailed the memory technology itself and the significant advantages it offers over DDR3 and GDDR5 memory. Today however we get to hear the story from an AMD perspective. And how the company intends to marry the new memory technology to products and all the benefits that will accompany that marriage. So without any further delay let's get straight into it.
3D Stacked High Bandwidth Memory, A Cornerstone For Next Generation GPUs And APUs At AMD
The Bandwidth Challenge And How To Overcome It
Traditionally performance and power efficiency have primarily been pushed by the progress of more advanced manufacturing processes in the semiconductor industry. Which enabled the creation of smaller, denser and more power efficient transistors as time went by, an observation that later became what is now known as Moore's Law.
AMD and SK Hynix spent seven years and poured an extraordinary amount resources to develop an entirely new memory standard for very good reasons. High Bandwidth Memory was born and exists today out of necessity. Traditional memory standards simply reached a point where they had become architecturally and economically not viable. This point is represented in the graph above at the intersection between the energy consumption of memory and the processor it is feeding.
Accelerators, especially bandwidth hungry ones such as GPUs, continued to scale rapidly. Because they benefited the most from the increasing transistor count and efficiency. Unfortunately memory standards did not and the more powerful these accelerator became the more memory bandwidth they required.
The situation ended up being that engineers would have to trade GPU power for more memory bandwidth to keep the GPU fed. AMD shared a similar graph nearly three years ago when the company's head of the die stacking program Bryan Black first discussed stacked memory and it's needed in the industry. And that's why the industry needed to look at other memory alternatives that would solve the performance and power efficiency challenges.
Memory standards such as GDDR5 hit a wall on several fronts. GDDR5 failed to continue to scale effectively in performance and power efficiency. Pushing the frequency of GDDR5 to attain more bandwidth meant sacrificing power efficiency. And designing processors with wider GDDR5 memory interfaces inflated both costs and power consumption.
The Real World Advantages of Stacked High Bandwidth Memory
GDDR5 also has a density limitation that would prevent its integration into high performance small form factor accelerators. High Bandwidth Memory on the other hand is vertically stacked, this in turn meant that the connections from one DRAM die to another were much shorter and thus more efficient.
Also because vertical stacking enables much greater densities there are immense area savings on the printed circuit board as a result. Enabling far more compact form factors.
The area savings extend to the DRAM die itself as well. HBM is far more compact than GDDR5.
Also unlike GDDR5, HBM is packaged along with hos processor / the accelerator on a single interposer. The closer proximity to the GPU enables significantly wider memory interfaces and reduces latency. The smaller, shorter connections also enable great power efficiency.
This means that that HBM will require a lower voltage to operate and is connected via considerably wider interfaces. Enabling significant memory bandwidth increases all the while keeping frequencies low for better power efficiency.
The end result is a 300% improvement in bandwidth per watt. Attained through significantly higher bandwidth and significantly reduced power. More interestingly, AMD estimates that 15-20% of the R9 290Xs 250W TDP is for the memory sub-system. Which means that AMD can reduce the memory power consumption from 40-50W down to 15W just by switching from GDDR5 to HBM. A 290X that utilizes HBM as a result would be a 215W GPU, rather than a 250W one. We expect to see this materialize with AMD's upcoming flagship Radeon based on the Fiji GPU.
AMD confirmed that it will be introducing an ultra enthusiast class graphics card featuring HBM this quarter. AMD is set to announce its 2015 product lineup at Computex on June 3rd and has promised "comprehensive details" about the products. We're hoping that Fiji ,the world's first GPU with stacked High Bandwidth memory, will be there and we can't wait.
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