AMD Instinct MI200 CDNA 2 ‘Aldebaran’ GPU Die Visualized – Up To 256 Compute Units, 8192-bit Memory Bus, 128 GB HBM2e Capacity
AMD's CDNA 2 powered Aldebaran GPU is headed for launch in the Instinct MI200 accelerator later this year. The GPU is going to feature an MCM design and will carry a massive amount of cores and memory. With all that we know about the chip so far, Twitter fellow, Locuza, has come up with a die block diagram of the full Aldebaran GPU and it looks like a beast.
AMD Aldebaran CDNA 2 GPU For Instinct MI200 HPC Accelerator Visualized - Up To 256 Compute Units, 128 GB HBM2e Memory
The block diagram is based on the latest details shared by Kepler_L2 for the CDNA 2 powered GPU. It was already confirmed that the Aldebaran GPU powering the Instinct MI200 will feature two dies, a secondary and a primary. The block diagram shows the two dies with each consisting of 8 shader engines for a total of 16 SE's. Each Shader Engine packs 16 CUs with full-rate FP64, packed FP32 & a 2nd Generation Matrix Engine for FP16 & BF16 operations.
Each die, as such, is composed of 128 compute units or 8192 stream processors. This rounds up to a total of 256 compute units or 16,384 stream processors for the entire chip. The Aldebaran GPU is also powered by a new XGMI interconnect. Each chiplet features a VCN 2.6 engine and the main IO controller.
The full config of Aldebaran is 2 dies x 8 Shader Engines x 16 Compute Units, but MI200 might be only 224 CUs enabled 🧐 https://t.co/RO7RptgYSk
— Kepler (@Kepler_L2) June 10, 2021
One interesting change relates to the vector units supporting full rate FP64 and packed FP32 ops.
64b DPP (Data-Parallel Primitives) were added.
The Matrix Units also support FP64 now, though I'm not sure if you get higher throughput vs. vector ALUs.
Both might do 128 ops/clk.
— Locuza (@Locuza_) July 1, 2021
Moving over to DRAM, AMD has gone with an 8-channel interface consisting of 1024-bit interfaces for an 8192-bit wide bus interface. Each interface can support 2GB HBM2e DRAM modules. This should give us up to 16 GB of HBM2e memory capacity per stack and since there are eight stacks in total, the total amount of capacity would be a whopping 128 GB. That's 48 GB more than the A100 which houses 80 GB HBM2e memory. This would really be a juggernaut of an HPC GPU but we also expect some really high power figures when it launches.
As for the product itself, Kepler_L2 states that the actual AMD Instinct MI200 accelerator will utilize a cut-down configuration comprising 224 CUs or 14,336 cores. That's around 14% lower cores than what the full Aldebaran GPU die has to offer.
Here's Everything We Know About AMD's CDNA 2 Architecture Powered Instinct Accelerators
The AMD CDNA 2 architecture will be powering the next-generation AMD Instinct HPC accelerators. We know that one of those accelerators will be the MI200 which will feature the Aldebaran GPU. It's going to be a very powerful chip and possibly the first GPU to feature an MCM design. The Instinct MI200 is going to compete against Intel's 7nm Ponte Vecchio and NVIDIA's refreshed Ampere parts. Intel and NVIDIA are also following the MCM route on their next-generation HPC accelerators but it looks like Ponte Vecchio is going to be available in 2022 and the same can be said for NVIDIA's next-gen HPC accelerator as their own roadmap confirmed.
In the previous Linux patch, it was revealed that l that the AMD Instinct MI200 'Aldebaran' GPU will feature HBM2E memory support. NVIDIA was the first to hop on board the HBM2E standard and will offer a nice boost over the standard HBM2 configuration used on the Arcturus-based MI100 GPU accelerator.
The latest Linux Kernel Patch revealed that the GPU carries 16 KB of L1 cache per CU which makes up 2 MB of the total L1 cache considering that each GPU will be packing 128 Compute Units. The GPU also carries 8 MB of shared L2 cache but carries 14 CUs per Shader Engine compared to 16 CUs per SE in the previous Instinct lineup. Regardless, it is stated that each CU on Aldebaran GPUs will have a significantly higher computing output.
Other features listed include SDMA (System Direct Memory Access) support which will allow data transfers over PCIe and XGMI/Infinity Cache subsystems. As far as Infinity Cache is concerned, it's looking like that won't be happening on HPC GPUs. Do note that AMD's CDNA 2 GPU will be fabricated on a brand new process node & are confirmed to feature a 3rd Generation AMD Infinity architecture that extends to Exascale by allowing up to 8-Way coherent GPU connectivity.
AMD Radeon Instinct Accelerators 2020
|Accelerator Name||AMD Radeon Instinct MI6||AMD Radeon Instinct MI8||AMD Radeon Instinct MI25||AMD Radeon Instinct MI50||AMD Radeon Instinct MI60||AMD Instinct MI100||AMD Instinct MI200|
|GPU Architecture||Polaris 10||Fiji XT||Vega 10||Vega 20||Vega 20||Arcturus (CDNA 1)||Aldebaran (CDNA 2)|
|GPU Process Node||14nm FinFET||28nm||14nm FinFET||7nm FinFET||7nm FinFET||7nm FinFET||Advanced Process Node|
|GPU Clock Speed||1237 MHz||1000 MHz||1500 MHz||1725 MHz||1800 MHz||~1500 MHz||TBA|
|FP16 Compute||5.7 TFLOPs||8.2 TFLOPs||24.6 TFLOPs||26.5 TFLOPs||29.5 TFLOPs||185 TFLOPs||TBA|
|FP32 Compute||5.7 TFLOPs||8.2 TFLOPs||12.3 TFLOPs||13.3 TFLOPs||14.7 TFLOPs||23.1 TFLOPs||TBA|
|FP64 Compute||384 GFLOPs||512 GFLOPs||768 GFLOPs||6.6 TFLOPs||7.4 TFLOPs||11.5 TFLOPs||TBA|
|VRAM||16 GB GDDR5||4 GB HBM1||16 GB HBM2||16 GB HBM2||32 GB HBM2||32 GB HBM2||64/128 GB HBM2e?|
|Memory Clock||1750 MHz||500 MHz||945 MHz||1000 MHz||1000 MHz||1200 MHz||TBA|
|Memory Bus||256-bit bus||4096-bit bus||2048-bit bus||4096-bit bus||4096-bit bus||4096-bit bus||8192-bit|
|Memory Bandwidth||224 GB/s||512 GB/s||484 GB/s||1 TB/s||1 TB/s||1.23 TB/s||~2 TB/s?|
|Form Factor||Single Slot, Full Length||Dual Slot, Half Length||Dual Slot, Full Length||Dual Slot, Full Length||Dual Slot, Full Length||Dual Slot, Full Length||Dual Slot, Full Length / OAM|
|Cooling||Passive Cooling||Passive Cooling||Passive Cooling||Passive Cooling||Passive Cooling||Passive Cooling||Passive Cooling|