Chip manufacturing giant Intel is considering deploying front and back side power delivery for its 1.4A manufacturing technology due to patterning errors in lithography, says a report. The limitations in lithography stem from the firm's need to catch up with Taiwan's TSMC and Samsung Foundry for transistor density on the 1.4A node. Through its 1.4A2 process, the firm aims to compete with TSMC's N2 and Samsung's SF2Z chip manufacturing process technologies.
Finer Circuit Size Forces Intel To Choose Dual Power Delivery For 1.4A2 Manufacturing Process, Says Report
In chip fabrication, power delivery typically occurs through the back side in order to reduce voltage drops and improve performance. Routing power through the backside, the region of the chip where transistors are assembled (called the front side), gains additional space, which improves transistor density and computing performance.
According to today's report, which comes courtesy of ETNews, Intel is considering shifting to dual-side power delivery with its 1.4 chip manufacturing process technology. The shift will be made on the technology's V2 version, and it is driven by the dimensions of the chip's lowest metal interconnect pitch (M0). ETNews believes that while for 14A, the M0 will be 28-nanometers, for 14A2, the pitch will drop down to 21-nanometers.
In semiconductor fabrication, the M0 pitch is the distance between the centers of two metal lines that are typically responsible for transferring signals between the transistors. A lower M0 enables more transistors to be packed within a chip, and more advanced chip fabrication technologies have had to rely on EUV to manufacture these circuits.
With the 14A2 manufacturing process technology expected to deliver Intel's standard 'half node' gain, ETNews' sources believe that the firm will have to rely on dual-side power technology with the process. By lowering the M0 to 21-nanometer with 1.4A2, Intel aims to improve the economics of using High NA EUV machines, though having grown transistor density, says the report.
However, due to the lower dimensions, the firm expects to face voltage drops in its through-silicon-vias (TSV) originally designed for backside power delivery due to the higher resistance of the interconnect wires. As a result, the firm is reportedly looking to rely on dual-side power delivery with the 14A2 process technology.
The sources add that since Samsung has already refined its gate-all-around (GAA) transistor architecture, it is running into fewer problems with the next-generation technologies. Similarly, TSMC has stabilized its N2 process technology family yields in 2025 and 2026 and will have shifted to shipping 1.4-nanometer products to the market by the time Intel starts 1.4A risk production. As a result, Intel is short on time, especially since it aims to ship 14A0.9 design kits to customers in October 2026.
About the author: Ramish is a seasoned technology writer and editor with more than a decade of experience. He specializes in semiconductor fabrication and market analysis. With a background in finance and supply chain management - via his bachelors in Finance and a micromasters in supply chain management from MIT - Ramish combines financial rigor with deep industry insight to deliver accurate and authoritative coverage.
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