AMD Zeppelin Processor with 32 x86 Zen Cores Spotted in Linux Changelog – EHP Variant Will Have Vega 10 Graphics with HBM2

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Feb 3, 2016

A very interesting report published by the New Citavia Blog confirms a codename we heard quite a long time ago: Zeppelin. To those who aren’t familiar with the name, Zeppelin is an MCM (Multi Chip Module) which will utilize AMD’s own custom interconnect to combine 32 Zen cores. Not much is known about this processor although it has popped up in various leaks over the course of the past few months.

AMD Zeppelin 32 Core MCMA modern zeppelin takes off. Image Credit URL.

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AMD’s Zeppelin processor with 32 Zen cores spotted in linux changelog

A Zeppelin is a type of a rigid body airship which is filled with a lighter-than-air gas. They were very popular in the early 1900s and a popular mode of transport. Unfortunately, the use of cheaply available hydrogen as the primary gas caused several accidents (most notably Hindenburg) over the course of the next few decades which caused them to be abandoned. Modern variants of the Zeppelin use Helium as the primary gas, which is just as light but not combustible.

Coming back to the actual topic at hand, the report in question quotes several lines of code published in a recent update bt AMD which can be found over at LKML.com:

AMD Zeppelin (Family 17h, Model 00h) introduces an instructions retired performance counter which indicated by CPUID.8000_0008H:EBX[1]. And dedicated Instructions Retired register (MSR 0xC000_000E9) increments on once for every instruction retired.

Signed-off-by: Huang Rui <ray.huang@amd.com>

arch/x86/include/asm/cpufeature.h   | 1 +
arch/x86/include/asm/msr-index.h     | 3 +++
arch/x86/kernel/cpu/perf_event_msr.c | 30 +++++++++++++++++++———–
3 files changed, 23 insertions(+), 11 deletions(-)

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+ core_complex_id = (apicid & ((1 << c->x86_coreid_bits) – 1)) >> 3;
+ per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;

The code is conveniently signed by an AMD engineer and confirms the name of the processor. An AMD research paper in the past has also referred to a very similar (if not the same) chip as an EHP or Exascale Heterogeneous Processor along with a diagram of the same. Which is basically an APU with the Zeppelin module included. The code present in this update also points to the expected 4 Zen core clusters and a total of 32 maximum CPUs which will be divided into core complexes consisting of 4 Zen cores each (8 logical cores thanks to SMT). Given below is a recap of what leaks have pointed out so far:

AMD is currently working on a Multi Chip Module that is code named Zeppelin. It is thought to contain 32 Zen cores tied together using AMD’s very own Coherent Fabric. The homegrown interconnect will support data rates of upto 100GB/s which is alot faster than what the PCIe interface sustains (around 15GB/s). Not only that but latency has been reduced from 500ns to an unknown but allegedly smaller number. It remains to be seen whether Zeppelin refers only to the Zen processors cluster or the MCM as a whole. The original leak by Fudzilla showed Vega 10 (previously Greenland) graphics connected by Coherent Data Fabric. High Bandwidth Memory (probably on a 2.5D interposer) was also included and clocked at 500 GB/s.

The Zeppelin and Vega 10 based MCM will feature 4 GMIs or Global Memory Interconnects (which constitute the Coherent Data Fabric I suppose) allowing the CPU to converse with the GPU at 100GB/s. The MCM itself will talk to the RAM at 100 GB/s as well – allowing for a very HSA friendly environment and minimum bottleneck throughout the whole process. Each Zen core will be capable of running two threads (thanks to the company’s shift to Simultaneous Multi-Threading). The processor is thought to have 4 DDR4 channels with a capacity of 256GB per channel.

What we do know for sure (thanks to a published research paper by AMD) is that the Zeppelin EHP variant will utilize the next generation Vega 10 graphics, although the exact core count remains unknown. The diagram published by AMD points towards the MCM divided into two compute and one graphic portions, which are manufactured separately and put together on the interposer later on in assembly (possibly at UMC’s Fab 12 foundry in Singapore, which is already used to assemble Fiji dies). So basically, AMD is fabricating the compute side of the Scale Heterogeneous Processor (EHP) in dies with 16 Zen cores each (4 core complexes), for a total of 2 computing and 1 graphics die assembled on the interposer (ignoring the HBM).