An AMD Zen based APU code named Raven Ridge featuring stacked High Bandwidth Memory - HBM - with 128GB/s of bandwidth and a large on-board GPU has been spotted. This came to light via a paper co-authored by one of AMD's highest ranking graphics engineers, Mike Mantor.
This isn't the first time that we've actually caught wind of AMD working on next generation products featuring HBM and die stacking technology in general. In fact, going all the way back to 2012 AMD's head of the die stacking program ,Bryan Black, gave a public talk titled "Die Stacking and the System" on die stacking technology and the pivotal role it's going to play in AMD's future products.
Black ,notably, is one of the leading engineers responsible for bringing HBM to market with AMD's Fiji GPU and the Radeon R9 Fury series. He is also still involved in all of AMD's products currently in-development that make use of die stacking technology.
AMD Zen Raven Ridge APUs Will Feature HBM - 128GB/S Of Memory Bandwidth Feeding A Large On-Board GPU
This latest paper is very interesting for a couple of reasons, the first is because it carries a very intriguing illustration that depicts a Zen APU, code named Raven Ridge, featuring a next generation fully memory coherent interocnnect, dubbed Onion3 capable of 50GB/S of total bandwidth. This chip fabric is based on the evolution of the AMD coherent memory technology in Carrizo which is in itself is an improved design of the Playstation 4 and XBOX ONE's interconnects. The illustration also makes mention of "more CUs" referring to graphics compute units, which indicates that Zen APUs will feature larger and more capable on-board graphics engines than what we've seen before.
Additionally, the Zen based APU is also shown featuring HBM memory with 128GB/S of bandwidth. Which is the amount of bandwidth a single 4-Hi stack of first generation HBM can deliver. And that's surprising, considering that in 2016 second generation HBM is expected to come to market with Nvidia's Pascal and AMD's Arctic Islands graphics chips. What's even more peculiar is that the compandy did not announce any Zen based APUs for 2016. Instead, at AMD's Financial Analyst Day Zen based APUs and enterprise class products were said to be coming in 2017.
Die Stacking Has Been In The Works For A Long Time At AMD
This isn't the first paper to describe an APU with 2.5 die stacking either. Back in 2014 another paper detailed AMD's "Fast Forward Project" to implement die stacking across the company's product lines. It demonstrated an APU with integrated stacked high bandwidth memory in addition to stacked non-volatile memory cells. These memory cells would act as the system's storage system and would essentially replace SSDs. This integration would offer several key advantages in compact low power mobile devices. The paper also described a fascinating new innovation called "Processor-in-Memory" which strives to push the performance of the device and reduce power. This is achieved by doing more of the computational work inside of the memory, instead of moving data across the chip and back which costs a lot of power.
More recently, going back to August of 2015 yet another paper came out demonstrating the use of stacked memory with a 32 core APU featuring a massive integrated graphics engine. Such an exascale heterogeneous "super-processor" would revolutionize the high performance computing space.
In a less official capacity we had also seen leaked documentation of another AMD processor with sixteen Zen cores, 32MB of L3 cache, 16GB of HBM, quad channel DDR4 memory interface and an integrated GPU based on the flagship Arctic Islands graphics chip "Greenland".
The first public mention of the AMD HPC APU was made by Junji Hayashi Consumer & Commercial Business Lead at AMD Japan. He took the stage at the PC Cluster Consortium in Osaka and laid out a rudimentary 5 year GPU and APU roadmap which included a high performance heterogeneous processor for the High Performance Computing market. This was all prior to CEO Lisa Su revealing the company's plans to introduce an HPC APU at the Financial Analyst Day in 2015.
Thus it's absolutely clear and no longer secret by any measure that we're bound to see AMD come out with APUs that feature integrated High Bandwidth Memory in addition to other integrated components via die stacking. It's simply the natural progression that has slowly been taking place over the past several years, culminated in the first ever such product "Fiji" last year. But that's only the first step of many to come. And we can't be more excited to see where die stacking can take the industry!