More Evidence Regarding AMD APUs Featuring High-Bandwidth Stacked Memory Surfaces
Evidence regarding stacked DRAM on next generation AMD APUs has surfaced once again which gives hints that the upcoming Carrizo APU or its successor will be the first APUs to enable high-bandwidth stacked DRAM design on-chip.
Evidence Regarding AMD APUs Featuring High-Bandwidth Stacked Memory Surfaces
It has been known for a while that AMD is sampling their first generation HBM (High Bandwidth Memory) and we can find official specifications in slides dating back to December 2013. While there was no mention of what product or application may make use of HBM back then, the latest slides from AMD’s official Fast Forward presentation talks regarding stacked DRAM specifically on APUs. The Fast Forward project’s objectives are to enhance the high volume APU architecture and investigate in next generation processor and memory tech for exascale and consume scale systems.
Within the presentation, you can find several references of stacked memory and new APU technologies such as HSA+, PIM (Processing In Memory) and Two Level memory. Some of these are already part of the current AMD APU family such as Kaveri which introduced several new features such as HSA on software and steamroller, gcn or hardware side.
The specifications of the HBM memory are interesting featuring a voltage of 1.2 – 2.5V with the DRAM Die density of 2 Gb per stack, each stack featuring 4 DRAM modules. The bus interface would be 1024-bit wide and the command interface would be the traditional DDR (GDDR for graphics units). Each stack would be made up of a logic die which will feature a 2.5D or 3D interface on which four DRAMs would be stacked. This stacked layer would be fused on the PCB just like the regular memory chips but would deliver high performance as the name suggests (HBM = High Bandwidth Memory). The following chart shows some difference between GDDR5 and HBM Stacked memory designs:
|Wccftech||GDDR5||2-Hi HBM ‘Stacked DRAM’||4-Hi HBM ‘Stacked DRAM’|
|Max Bandwidth Per Pin||7 Gbps||1 Gbps||1 Gbps|
|Max Bandwidth||28 GBps||64 GBps||128 GBps|
|Voltage||1.35 – 1.65||~1.2||~1.2|
|Layers||1||2 + 1||4 + 1|
Now the real question is, what application will be the first to feature HBM? It has long been known that at some point, AMD will start featuring HBM on their graphics processing units but will the next generation AMD APUs also feature this technology and whether the stacked memory will replace the traditional DRAM (Main memory) or be used for the iGPU. The block diagram as seen in the slide shows that the stacked memory will specifically be used to deliver high memory bandwidth and since the iGPU on AMD APUs which share the same GCN architecture as the discrete graphics cards, it will be the one to benefit the most out of this design. HSA+ will also be a core technology of AMD APUs in the future delivering an enhanced coherency between the APU architecture offering reliable and power-efficient computing.
AMD’s Carrizo APU is currently planned for launch next year, featuring the x86 Excavator core architecture and the latest GCN core architecture. Details regarding the mobility Carizzo APU platform were unveiled a few days ago which showed a true SOC design on the mobility front while the platform will continue to support DDR3 memory. The slide mentioned that Carrizo “Mobile” will also feature higher memory efficiency which will deliver better performance throughput since APUs are generally bandwidth starved, Delta color compression and feature full HSA support with a high-performance integrated bus for graphics and DRAM. So whether or not Carrizo “Desktop” features HBM remains a mystery but we can expect that AMD’s 20nm products that are arriving in 2015 will start implementing stacked memory.