The Taiwan Semiconductor Manufacturing Company (TSMC) is unlikely to experience significant competitive pressures to its advanced packaging and chip manufacturing technologies, says a research report from Citibank. In its coverage, the bank's analyst points out that the capacity for TSMC's advanced CoWoS packaging technology could grow significantly due to tailwinds from AI in 2026 and 2027, with other technologies such as system on integrated chips (SoIC) and chip-on-panel-on-substrate (CoPoS) can drive demand in the coming years.
Intel's EMIB-T Packaging's Success Is Dependent On ABF Substrate, Says Analyst
Over the past couple of weeks, multiple reports have suggested that not only is Intel aggressively marketing its EMIB-T packaging technology, but also added that big ticket technology names such as Google are interested in the technology for their AI chips. As opposed to standard packaging technologies which rely on a silicon interposer to transfer the signals between the chip and the board, EMIB relies on an organic substrate.
The use of the substrate allows for several benefits, such as lower costs. A variant of EMIB, called EMIB-T, relies on through-silicon via (TSVs) to connect the two components. Through these, Intel claims that its EMIB-T packages reduce leakage over the standard EMIB packages as they conduct current directly from the board to the chip and vice versa.
Analyst Asserts TSMC's Position Will Remain Solid In AI Industry
According to the Citi analyst, since EMIB depends on ABF (Ajinomoto Buildup Film) substrates quite a bit, its success will be dependent on the maturity of the ABF ecosystem. Given the production constraints that TSMC is facing for its CoWoS packaging technology, the analyst adds that whether ABF suppliers are able to scale up production will also determine the scalability of EMIB.
Another competitive factor for TSMC that is often discussed in the market is Intel's 18-A process. Recent news has suggested that Apple is aggressively interested in the technology, but the Citi analyst believes that while tape out is a typical industry practice, it does not guarantee future large-scale mass production. The research focuses on AI and HPC chips to emphasize that designs for chips planned for 2027 and 2028 have already been finalized.
About the author: Ramish is a seasoned technology writer and editor with more than a decade of experience. He specializes in semiconductor fabrication and market analysis. With a background in finance and supply chain management - via his bachelors in Finance and a micromasters in supply chain management from MIT - Ramish combines financial rigor with deep industry insight to deliver accurate and authoritative coverage.
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