TSMC’s True EUV Lithography Will Be On N5 Node For 2x Transistor Density
As we head to September, one thing is for certain. Apple’s 2019 iPhone 11 lineup will feature a brand new processor that is manufactured on TSMC’s N7+ node. The N7+ node will use Extreme Ultraviolet lithography (EUV) for certain layers on the A13 and provide the chip with performance and power efficiency improvements over its predecessor, the A12. TSMC, however, is looking at the future. The company is aggressively developing next-generation lithography techniques, packaging methodologies and performance nodes. Today we’ve got a lot of details on what to expect from the Taiwanese fab for the next couple of years. Take a look below for more.
TSMC’s N7+ Process Will Use EUV For Select Layers – Taiwanese Fab Will Implement More Layers Through EUV In The N6 Fabrication Process
While most folks know only about TSMC’s N7 and N7+ nodes, the reality is that the fab has others as well. These other nodes represent a shift between generations of the different manufacturing process developed by the company and are an extension of their predecessors too.
Today we’ve got details for six of TSMC’s performance nodes and five packaging techniques. The nodes extend up to the year 2023, and the techniques will extend from mobile SoCs to 5G modems and front-end receivers. TSMC had a busy VLSI Symposium earlier this year, where it showed a custom-built octa-core A72 chiplet capable of 4GHz frequency at 1.20V. TSMC also introduced tungsten disulphide as a channel material for conduction at 3nm and beyond.
Now, after TSMC’s presentation at this year’s Semicon West, the good folks over at Wikichip have consolidated the company’s process node and packaging plans. While the N7+ is TSMC’s first EUV based node, chips fabricated through this technology are not TSMC’s most advanced silicon utilizing EUV. For more details on the N7+, take a look here.
TSMC’s First ‘Full’ Node After The N7 Is The N5 With Three Intermediary Nodes Leveraging On N7’s IP And Design
Succeeding the N7 node is TSMC’s N7P process, which is a DUV-based optimization of the former. The N7P uses N7’s design rules, is IP compatible with N7 and uses FEOL (Front-end-of-the-line) and MOL (Middle-of-line) improvements to deliver either a 7% performance improvement, or a 10% power efficiency gain.
The N7+ is TSMC’s first fabrication process to use EUV, and it doesn’t use the advanced, low-wavelength lithography for all layers. As a result, the design process improves marginally over the N7P. TSMC’s first true EUV implementation for the N7 is the fab’s N6 processing node. The N6 is design and IP compatible with the N7, but its main strength lies in cell abutment.
This will be TSMC’s first node to use continuous poly over diffusion edge process features to lay out logic blocks, allowing register path optimizations and reducing dead time. The improvements will let processors using the N6 have an 18% density improvement over chips made by the N7+. N6 is scheduled for risk production in 2020.
Risk production for TSMC’s 5nm node referred to as the N5 kicked off in April 4th, and a single report from Taiwan suggests that the process will end up in mass production after next year (2021). TSMC expects production to ramp up in 2020, and the fab has invested extensively in developing the process, as the N5 is the N7’s first true successor, and the chips manufactured through the process will use EUV for the majority of their layers.
Chips made using the N5’s fabrication principles will be twice as dense (171.3MTR/mm²) as those made through the N7, and they will allow users to eke out either 15% more performance or reduce power consumption by 30% over the N7. FEOL and MOL optimizations will, however, take place on the N5P. Through these, the N5P will improve performance by 7% or power consumption by 15%.
By the looks of things, TSMC has planned its future actions astutely, and the fab isn’t hesitant to share details of its plans. The N5 node is the one that we all need to watch out for, since chips manufactured through this node will generate sufficient computing power at a smaller area to allow TSMC’s chiplet applications to come fully in play.
Thoughts? Let us know what you think in the comments section below and stay tuned. We’ll keep you upated on the latest.