TSMC’s Custom Built, Octa-Core A72 Chip Reaches 4GHz At 1.20V

Jun 26, 2019
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Over the past few years, Taiwanese fab TSMC has come into the international spotlight, as chipmaker Intel’s fortunes seem to be stuck. TSMC’s has a busy couple of years experimenting with EUV, and now, the fab has presented several research papers at the VLSI (Very-large Scale Integration) Symposium held in Japan. Take a look. below for more details.

Taiwanese Fab TSMC Presents Research Papers Highlighting A Design For A 7nm Chiplet With ARM A72 Cores Using CoWoS Packaging Technology

At the symposium, TSMC introduced several research papers which cover technologies ranging from pre-package soldering for eMRAM to a new chiplet design based on ARM’s Cortex A72 cores. TSMC also introduced a research paper on tungsten disulphide; a channel material that the fab believes will allow for improved electron flow at 3nm and beyond due to improved two-dimensional electron switching. This tungsten disulphide short-channel transistor is manufactured through chemical vapor deposition directly on the silicon substrate, as opposed to earlier processes that required a sapphire intermediary.

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The real highlight of the conference, however, as far as TSMC is concerned, is the company’s research paper titled ‘A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High-Performance Computing’. This research is intended to demonstrate that limitations with packaging and interconnects that are inherent in any chiplet design can finally be overcome. TSMC hopes to overcome these through its CoWoS (Chip-on-Wafer-on-Substrate) packaging and BiDir Interconnect Mesh Bus.

TSMC’s design starts from a single chip with two chiplets on board. Each chiplet die is 4.4 mm by 6.2 mm with four Cortex A72 cores present. The cores have a custom L1 cache, and two 1 MiB L2 cache blocks on the die. An additional high-density bitcell 6 MiB L3 cache is also present. The cores can reach 4.0GHz at 1.20V, and 4.20 GHz at 1.375V. Additionally, the 1968-bit wide on-die mesh interconnects are capable of operating above 4GHz, and six of these are present on each die.

The two chiplets are connected to each other through TSMC’s Low-voltage-In-Package-INterconnect (LIPINCON). Each of these PHYs measures 0.42mm x 2.4mm, and can reach data transfer rates of 8Gb/p/s (Gigabit-per-pin-per-second) through a 2:1 multiplex function. LIPINCON also provides 0.56pJ/bit power efficiency and 1.6TB/s/mm² bandwidth density and 320GB/s bandwidth. It’s also important to note that more than two chiplets can be used with this design.

Through using CoWoS, TSMC is able to drive down power consumption for the chiplets, and TSMC has used a micro-bump pitch of 40µm in this design, and the two dies are separated by 100µm. These numbers put the Taiwanese fab ahead of Intel, and if TSMC continues its current trajectory, then it could very well expand its presence in the market in the future. Thoughts? Let us know what you think in the comments section below and stay tuned. We’ll keep you updated on the latest.

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