TSMC Announces Details For 7FF+ Using EUV And Its N7+ Node; Will Deliver 50 Tapeouts For Basic 7nm, Make Small Gains With 7nm+

TSMC 10nm FinFET production

Dynamics in the processor market are set to change as Moore's Law slows down following the Dennard Scaling. Intel is struggling to make the big jump to 10nm, and while the Santa Clara chip giant is in the lead right now, it's current slowdown isn't helping anyone. On that note, Taiwanese Fab TSMC has detailed its 7nm+ and 5nm nodes today, expecting to produce 18 million wafers by the end of this year. Take a look below to find out more details.

TSMC Announces Mass Production For 7nm And 5nm Chips; Provides New Details For 5nm And Expects To Produce 18 Million Wafers By The End Of 2018

It's no secret. While manufacturers are still able to shrink die sizes, they can't match performance gains witnessed a handful of years back. In addition, the smartphone market changes dynamics, as power efficiency gains start to play a more important role. As die sizes continue to shrink, TSMC and Samsung need to make the jump to EUV. At this point, the companies are taking different paths; Samsung's dubbing its non-EUV 7nm as 8nm and TSMC intends to upgrade to a 7FF+ next year.

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With that in mind, the Taiwanese fab has revealed some important details for its 7FF+ and 5nm plans. TSMC has confirmed that it's in volume-production with basic 7nm. In addition, the manufacturer also sounds very optimistic for the advanced 7FF+ that will use Extreme UltraViolet Lithography. This, according to the fab, will ramp up early next year.

TSMC's basic 7nm node has entered volume production and the fab expects to deliver at least 50 tapeouts by the end of this year. The process delivers 40% power efficiency and 37% area reduction over its predecessor 10nm FinFet. While these might sound impressive, the company's expected numbers with 7FF+ will clearly demonstrate a slowdown of Moore's Law.

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TSMC's Jump From 7FF To 7FF+ Using EUV Will Demonstrate How Hard It Is To Maintain Gains; 10% Power Efficiency And 20% Density Increase With Little Performance Gain Expected On The N7+ Node

TSMC's provided critical details for both the N7+ node and 5nm. The fab confirms validation of the N7+'s IP in silicon. The node will set the base for its 7FF+, manufactured using Extreme Ultraviolet Lithography. However, while it confirms implementation, several blocks of the N7+ will not be ready before the end of this year. These include 28-113G serdes, embedded FPGAs, and DDR5 interfaces.

Finally, the N7+ will provide only 10% power efficiency and 20% density increase over its predecessors 7FF. Moving towards 5nm, it promises 1.8x density of 7FF, a power reduction of 20% or a performance boost of 15%. EUV will prove critical in this scaling, for both N5 and N7+. Many IP blocks for 5nm will not be validated until next year. These include PCIe Gen 4, DDR4 and USB 3.1

TSMC also announced that it sustained production at 250W in April and plans to increase this to 300W this month. Right now, the foundry is operating at 145W daily levels, but its management sounds optimistic. Thoughts? Let us know what you think in the comments section below and stay tuned. We'll keep you updated on the latest.

News Source: EE Times

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