Intel Skylake Speed Shift Technology - Power Performance and Energy Efficiency
Up till Skylake, Intel has made dramatic changes to the power management systems found on their new chips. With Skylake, Intel takes a step forward by reducing power consumption and enhancing efficiency by taking away a few things and integrating a few new things. We know that a Skylake SOC can consist of 2-4 CPU cores, graphics cores, media IPs, a ring interconnect, cache and ISA (Integrated System Agent). An SOC design can further more consist of an on-package PCH and eDRAM. Intel simply adds in a new unit known as PCU (Package Control Unit) that is a power management logic and controller firmware that can track internal statistics of the SOC, collects internal and external power telemetry (iMon, Psys) and can even interface to higher power management hierarchies such as OS, BIOS, EC, graphics driver and DPTF.
Intel also incorporates several hardware level P-states which divides the energy and frequency demands into several tiers and controlled by the operating system. This demand base algorithm of P-State is a bit slower as it leads into several P-states from energy efficient mode (min V) Pn, to P1 and P2 states and then P0 -1 core or P0-2 cores that deliver the highest frequency when demanded. With Skylake, Intel has housed their latest speed shift technology (hardware P-state) that is a highly dynamic power management system that can configure multi-core designs, AVX and accelerators to enhance efficiency. The power gating system is a lot more brute on Skylake that can even shut down AVX2 completely when its not in use.
By exposing the entire frequency range, Skylake will deliver smarter power management by allowing small form factors with larger turbo frequency range and finer grain, micro architectural observability by allowing both the hardware and software to share power and performance control. The lowest frequency with the latest management is now set to 100 MHz on Skylake.
Intel Skylake Hardware P-States:
• Operating system directed minimum quality of service, directive of desired performance and energy performance balancing
• Autonomous algorithms that self-manage the P-states within the OS directed range (normally full min to max range)
• Detecting user interaction and accelerating responsiveness
• Energy efficient race to halt
• Core duty cycling
• The power and power delivery controls including: PL1/2/3/TDC/Psys
Contents
You can find additional information about our hardware review process and ethics policy here.
