Intel’s Broadwell to Skylake uArch Transition Will Be As Big As Prescott to Conroe
Some of you might remember my exclusive piece a few weeks back which stated that Intel is preparing something big and disruptive with the Skylake micro-architecture. Well, today I have a third party report from Bitsandchips.it that confirms our month old report. The report states that the jump from Broadwell to Skylake will be as big as the jump from Prescott to Conroe (that’s Pentium 4 to Core 2 for the nomenclature averse) which is a very impressive jump.
Architectural Jump from Broadwell to Skylake is the same as Pentium 4 to Core 2
Some preliminaries are in order for this piece I think. One of the first major changes we exclusively revealed about Skylake was the removal of the FIVR (fully integrated voltage regulator) from the die. While at the time we thought it was due to the redundancy not being justified and the heat envelope of the package being raised, it would now appear there might have been more to it than just that. While early speculation pointed to yield problems and the cost of the FIVR not being justified, the fact that Intel was actually undergoing a complex architectural change might be the actual answer.
Here is an excerpt about Intel’s antics with Skylake and its NDAs from my original piece:
One of the surprising things that our source mentioned was that Intel has always been fairly lenient about information after the NDA is signed. However, this time, for the first time in many years, they simply refuse to divulge the slightest information even under NDA. This ‘above top secret’ attitude seems out of place since the process was already introduced with Broadwell and is supposed to be just a ‘Haswell-equivalent’ for Broadwell. Something that definitely appears to not be the case.
The first thing the report claims is that the uArch jump from Broadwell to Skylake will be as significant as the jump from the Pentium 4 (Precott) to the Core 2 (Conroe). That basically means that Skylake wont simply be a Haswell-equivalent of Broadwell and will have a pretty big IPC jump. The report then goes on to say that Intel abandoned the FIVR primarily because of the high complexity of the new project. Intel’s C++ Compiler is also being reivsed to take advantage of new features that have been integrated into Skylake. Blue is currently focusing on getting the uArch completely bug free – one possible explanation for the delay.
It is worth noting here that while the IPC gains could be very high – the actual performance gains will not be as high if the clock speeds are not high simultaneously. One of the hunches I have (Read: speculation) is that Intel’s launching Skylake-S early to take advantage of the buffer zone while taking their time with Skylake-K so that any bugs that hinder clock speed have been ironed out. That would involve solving the TDP problem and eventually rolling out some very impressive unlocked processors. I must say anticipation for Skylake is at an all time high, so lets hope Intel doesn’t concentrate primarily on the mobile platform and forget the actual audience of high end CPUs: the desktop users.