Intel’s XBM Memory Takes Aim At HBM4, Promising 32 GT/s Speeds And Lower Costs Through UCIe Links

Intel has published a new patent on its XBM memory, which is proposed as a replacement for HBM4, offering much higher bandwidth capabilities.

XBM vs HBM: Intel's New Proposed DRAM Solution Extends To 32 GT/s Speeds, While Reducing Costs Through UCIe Links

HBM continues to be the standard for AI accelerators, but more recently, we have seen LPDDR memory being used to overcome shortages, prices, and power associated with the standard.

Intel's past attempts at DRAM, such as HMC (Hybrid Memory Cube) and MCDRAM, faced various issues and never came to market, but with XBM, Intel is course-correcting its DRAM ambitions, and along with ZAM, the company may once again see a return to the DRAM segment, & this comes at a time when the entire memory segment is facing heightened shortages.

In this week, an Intel patent application was published, revealing its proposed Cross-Batch Memory (XBM), an ultra high-bandwidth memory that offers some significant improvements over the current standard, which could be a direct competitor to HBM4 in the near future. pic.twitter.com/RPKTZ9XwzS

— Underfox (@Underfox3) July 5, 2026

On one hand, LPDDR is more efficient and offers higher capacities, but at the same time, it comes with a bandwidth problem. Qualcomm is fixing this problem with its HBC technology, and Intel has already proposed an alternative to HBM, called ZAM (Z-Angle Memory). These solutions are yet to enter the commercialization stage, but it looks like Intel has a new proposal for an HBM-tier competitor, called XBM.

Embodiments describe ultra-high bandwidth memory (often referred to in discussions as XBM or similar next-gen HBM alternatives) using backend transistors. A memory structure includes a package substrate, an optional base die, and a stacked memory die configuration. Each memory die in the stack uses one-transistor, one-capacitor (1T1C) backend dynamic random access memory (DRAM). This moves transistors to the back-end-of-line (BEOL) metal layers for improved area efficiency, higher TSV density, and significantly boosted bandwidth compared to traditional front-end transistor DRAM.

via Patent (Ultra High Bandwidth Memory With Backend Transistors)

According to the latest patent filed by Intel, XBM is a cross-batch memory, which is a DRAM block that is connected to a UCIe I/O block that operates at 32 GT/s. The goal is to match the footprint of HBM4 with each XBM memory holding a die capacity of 0.5 - 5.0 GB. The IO is routed through the base die.

Each sub-channel consists of 12 Datablocks, & there are up to 96 DB's on an 8-high XBM solution, and 192 DB's on a 16-High XBM solution. These channels operate at 2 GHz frequencies. One of the advantages of XBM is that it can be implemented in a variety of package options, including MoP (Memory-on-Package), where it could offer higher bandwidth and capacities in smaller form-factor solutions.

Each memory die uses 1T1C (one transistor, one capacitor) backend DRAM. Transistors are fabricated in the back-end-of-line (BEOL) metal layers rather than front-end silicon. This dramatically improves area efficiency, allowing more space for TSVs and higher overall density/bandwidth.

Architecture Features:

• Alternating sub-channels and TSV "gutters" for efficient data routing.
• High-bandwidth interconnect (HBI) connections on both sides.
• Built-in self-test (BIST), redundancy, and repair capabilities (including spare channels).
• UCIe (Universal Chiplet Interconnect Express) interfaces for high-speed data funneling.
• Optional base die with test/controller/debug logic or fully distributed logic across the stack (no base die in some variants).

According to the details, XBM should match or exceed the HBM4 footprint while targeting higher bandwidth and capacity through denser TSV usage and backend transistors. XBM is aimed at overcoming HBM limitations (TSV area overhead, routing complexity, power).

The new memory architecture is expected to support significantly higher total bandwidth via more parallel sub-channels and efficient stacking (speculative estimates in coverage suggest potential 2x improvements, though the patent itself does not quote exact metrics like GB/s or capacity targets). XBM should be targeting a 2030+ timeline for commercialization, which is in line with what we heard about ZAM.

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