The Hybrid Memory Cube technology was one of the earliest concepts of stacked-DRAM alongside with the High Bandwidth Memory we know and love. While its implementation (so far) has been limited to niche products such as the Xeon Phi coprocessors, it nonetheless remains a very interesting piece of tech - and a potential rival of HBM. Just recently, Micron has revealed that it will unveil the HMC 3.0 standard sometime in 2016 - a change that will result in significant improvements over the older version.
HMC 3.0 from Micron landing in 2016 - Specification currently unknown
Let's talk a bit about its historical use. HMC is being used in conjunction with Knight's Landing cores in Intel's Xeon Phi coprocessors. Using the 2.5 D stacking that should now be pretty familiar for our readers, Intel surrounds the Xeon Phi die using a Micron-Intel custom made, super-high bandwidth, parallel path interface that makes the HMC appear as if its on the die. Infact it will act more or less like an L3 cache worth 16GB. The Hybrid Memory Cube used in the Knights Landing Xeon Phi package will feature upto 2000 TSVs and an ASIC at the base of the HMC to manage the DRAM package.
It promises more than 5 times the bandwidth of DDR4 RAM and more than 15 times the bandwidth of DDR3 Ram. Because Intel is using a customized Micron 16GB HMC solution (they already have 2GB and 4GB variants) and a customized interface the bandwidth will be 500GB/s.
“To be frank, we cannot achieve the applications and system needs without developing a really good packaging technology,” said Scott Graham, Micron’s general manager of Hybrid Memory at the Intel Developer Forum last month. “We’re not going to achieve these bandwidth capabilities. We’re not going to achieve the reliability needs. We’re not going to overcome some of the scaling challenges without developing some of these new technology methods. If you look at Hybrid Memory Cube, that’s been the lead vehicle for Micron in order to develop these package technologies for future emerging memories.”
Now, Open-Silicon is one of the founding members of the Hybrid Memory Cube consortium and is also the one that licenses the use of the memory type. It is also through them that we know the primary difference between HMC 1.0 and 2.0. Specifically, the upgrade to 2.0 includes a jump from 15Gbit/s to 30Gbit/s (not the total effective throughput of the HMC). Speeds upto 480GB/s are achievable with 1TB/s now in the horizon. The controller supports networking of upto 400Gb/s (increased form 100Gb/s). Since the speed of the HMC will naturally increase with 3.0 we could be looking at anywhere from 45 Gbit/s to 100 Gbit/s depending on the amount of advancement made.
HMC is currently only available in 2GB and 4Gb variants. Currently each HMC has 4 memory stacks with 1 control die (similar to 4+1 or 4 Hi HBM) and TSVs are used to connect them. It is also very much possible that HMC 3.0 overcomes this barrier and allows much higher density stacks resulting in products with even higher memory. If HBM is any indication, 8-Hi stacks with 8Gb variants should definitely be on the table.