Intel CEO’s Rumored Taiwan Visit Can Involve Bid For TSMC’s Latest Chip Technologies

Ramish Zafar

This is not investment advice. The author has no position in any of the stocks mentioned. has a disclosure and ethics policy.

Intel Corporation's chief executive officer Mr. Patrick Gelsinger is set to visit Asia next week as part of the company's plans to outsource some of its chip fabrication needs. The report comes the courtesy of Bloomberg, who speculates that Mr. Gelsinger will visit Taiwan and Malaysia, as part of his trip to highlight the importance of the two countries in Intel's efforts to turn around its recent misfortunes and regain the ability to mass produce semiconductors with advanced manufacturing processes. Intel is widely believed to source parts of its CPUs and GPUs from Taiwan's Taiwan Semiconductor Manufacturing Company (TSMC), with the American chipmaker's current roadmap expecting to achieve production parity with TSMC's advanced technologies by the second half of next year.

Rumor Of Intel Chief's Visit Follows Earlier Report Of Company Looking To Finalize 3nm Contract With Taiwanese Fab

Today's report is not the first time a trip by Intel's management to Taiwan has surfaced in the rumor mill. It follows one that surfaced last week from Taiwan soon after Mr. Gelsinger highlighted that he believed the region's precarious geopolitical nature was not favorable for the global semiconductor industry which has seen its firm pioneer leading technologies but slow down the pace in recent years.

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The first report speculated that Intel's management would visit the island to finalize a contract for 3-nanometer (nm) products with TSMC. This technology, once it enters mass production next year according to estimates from TSMC CEO Dr. C.C. Wei, will be one of the most advanced chipmaking processes in the world. Alongside TSMC, Korean chaebol Samsung Group and Intel itself plan to have similar technologies on the production lines by the second half of next year.

Samsung's optimism has seen it publicly announce that the first 3nm products off of its lines - which use a newer transistor design - will make their way to customers in the first half of next year. Neither TSMC nor Samsung Intel have provided a comparable timeline.

Samsung Foundry's diagram shows the evolution of a transistor from FinFET to GAAFET and then MBCFET.The 3nm process from the Korean company will utilize GAAFET transistors, which it has developed in partnership with International Business Machines Corporation (IBM). However, Samsung's production efficiency has raised some questions in the industry for its previous chip technologies. Image: Samsung Electronics

While Bloomberg is less forthcoming with details in its report, the one from DigiTimes hinted that the primary agenda on a high level meeting between Intel and TSMC will be to ensure a steady supply of 3nm chips for Intel. The Taiwanese publication speculated that Intel will aim to ensure that its orders are not affected by the Cupertino technology giant Apple Inc. Apple is widely believed to have the first 'dibs' on TSMC's latest products, and the limited amount of the fab's initial 3nm output will see fierce competition between companies.

This output should not exceed 40,000 wafers per month throughout 2022 believes DigiTimes, and interestingly, Intel might also kick off discussions with TSMC for the latter's N2 process technology family. While the industry has speculated on longer development times for 3nm, TSMC outlined earlier this year that customer interest for N3 was more than twice as strong, when compared to the predecessing N5 technologies, of which the company has received more than double the tapeouts for N3.

The N2 family will be TSMC's next-generation chip technologies that will succeed 3nm. The company's senior vice president of operations Mr. Y.P. Chin stated in June that his company was in the process of acquiring land to build the production sites that will ultimately be responsible for N2 production.  A planned 2nm facility in Taiwan's Taichung city has sparked local concerns for copius water and power usage by semiconductor fabrication.

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