TSMC Shares Major EUV Chipmaking Lead and Plans For 2nm Production Plant


During the Taiwan Semiconductor Manufacturing Company's (TSMC) 2021 Online Technology Symposium, the company's senior vice president for operations, Mr. Y.P. Chin, shared important details for his company's chip manufacturing capacity and progress with extreme ultraviolet (EUV) lithography. TSMC houses half of the world's EUV machines and was responsible for moving more than half of global silicon wafers manufactured through the latest technology, outlined Mr. Chin. He also shared details about TSMC's manufacturing prowess with its latest technologies and the fab's progress with its 3nm, 2nm manufacturing facilities alongside a planned chip fabrication campus in Arizona.

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During the symposium, the executive started his keynote by highlighting that TSMC is on track to maintain a 30% compound annual growth rate (CAGR) for its production capacity of advanced manufacturing processes. These processes include the company's 16nm, 7nm and 5nm manufacturing processes, with 5nm being the latest technology available to TSMC's customers and consumers for use.

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He then shared the plans for TSMC's production capacity plans for the 7nm and 5nm nodes. According to Mr. Chin, the fab is on track to increase 7nm production capacity by four times at the end of this year over the levels in 2018. For 5nm, TSMC plans to double its production capacity over last year, and the fab's long-term plans for the node involve a 4x capacity increase in 2023 over last year's levels. These plans are for TSMC's N7 and N5 process families, respectively, and they include processes such as the N6 and N4. N4 risk production is set to start later this year, according to TSMC's SVP R&D Dr. Y.J. Mii.

Sharing defect densities, or the proportion of end-products unsuitable for use, TSMC's operations lead outlined that for his company's N5 and N4 processes, defect densities have dropped over the 7nm (N7 and N6) process families, with the data for N4 reflecting early-stage defects.

An excerpt from TSMC's SVP Operations Mr. Y.P. Chin at the company's online technology symposium earlier today highlighting the fab's defect densities for its N5 and N4 processes. Image: TSMC 2021 Online Technology Symposium/Taiwan Semiconductor Manufacturing Company

During his keynote, Mr. Chin also shared key statistics for TSMC's EUV production capacity. An aggressive reduction in circuit sizes required by modern chipmaking processes requires these machines, which use light rays with reduced wavelength. This also reduces overall defects, as highlighted by the graph above, which shows TSMC's N5 process, which uses more EUV layers, as having lesser defects than its predecessors.

According to the executive, TSMC accounted for 50% of the global installed EUV production base. Furthermore, and more importantly, the fab was responsible for shipping 65% of all the semiconductor wafers globally, which had circuits printed on them with the latest machines. The latter percentage, referred to as 'EUV' wafer move, stood at 60% during the first half of 2020.

Mr. Chin also revealed during today's event that TSMC plans to increase its capacity for EUV pellicles and the time duration that a mask can be used. Image: TSMC 2021 Online Technology Symposium/Taiwan Semiconductor Manufacturing Company

Delving deeper into the fab's EUV capacity, Mr. Chin stated that TSMC expects to double its EUV pellicle capacity and increase mask lifetime to mirror DUV (Deep Ultraviolet lithography, EUV's predecessor) by the end of this year. In the chip fabrication process, a mask is a blueprint of the circuits that a machine prints on a silicon wafer, and a pellicle is a cover designed to protect the end-product design from any defects due to pollutants or impurities. EUV masks are generally limited to a set number of wafers, following which a new mask is needed, and TSMC's mask lifetime increase will reduce the manufacturing cost of its latest chip processes.

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Sharing plans for TSMC's construction progress and plans for its next-generation 3nm process and the N2 node, the executive outlined that phases 5, 6, 7 and 8 of its Fab 18 in its Tainan site will be responsible for N3 production. TSMC also plans to expand its N5 production at the Tainan campus by building the Fab 18's phase four. The fab is currently responsible for manufacturing N5 products, and the expansion will enable the company to meet its long-term objective of increasing N5 production.

He also confirmed that TSMC plans to build a new chip fab for manufacturing semiconductors with its N2 process family, which, based on precedent, should cover its 2nm chip manufacturing process. This plant will be located in Taiwan's Hsinchu sector, and it will be dubbed Fab 20. The first phase of its construction plans includes four phases, and Mr. Chin stated that his company is currently acquiring land for the project.

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