TSMC Shares 3nm Power and Performance Gains & Details For Potential 2nm Design

Dr. Y.J. Mii during his keynote at TSMC's 2021 Online Technology Symposium. Image: TSMC 2021 Online Technology Symposium/Taiwan Semiconductor Manufacturing Company

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The Taiwan Semiconductor Manufacturing Company (TSMC) shared the latest details about its leading-edge manufacturing nodes today. TSMC's statements came at its 2021 Online Technology Symposium, which kicked off earlier today. At the event, TSMC's senior vice president of research and development, Dr. Yuh Jier Mii, shared details about the fab's latest semiconductor manufacturing processes, including its N6, N5, N4 and N3 process nodes. These include information about the processes' defect densities, yields and production timelines.

TSMC Outlines Strong Customer Adoption For It N3 (3nm) Process Node – Expects New Tape Outs To Be Double Over Predecessor

During his keynote, Dr. Mii started by highlighting that in 2020, TSMC increased its research and development spending and headcount to stand at record levels. He also outlined that since the fab first introduced its 7nm process in 2018, it has shipped more than one billion chips manufactured by it. The 7nm node has proven crucial for chip designer Advanced Micro Devices, Inc (AMD), whose central processing units (CPUs) and graphics processing units (GPUs) were among the first to use the manufacturing technology. This enabled the company to increase its market share against the larger Intel Corporation and bring its products at a level with the larger company over time.

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Commenting on TSMC's N6 process node, Dr. Mii outlined that this process improves logic density by 18% over its N7 (7nm) process and uses more layers with extreme ultraviolet lithography (EUV) during the production process. He also stated that the N6 node would account for roughly half of TSMC's N7 output by the end of this year, as products using the process are in high-volume production. Even though the process will print finer circuits compared to N7, Dr. Mii also confirmed that the defect density for N6 equals N7 and that EUV usage enables TSMC to reduce manufacturing time.

Lower manufacturing time is a crucial achievement for TSMC, as the fab saw this time duration increase as it introduced the 10nm and 7nm process nodes after the 14nm and 16nm nodes. While the N6 process improves density and manufacturing over the N7, it is still classified as the latter's 'sub-process' due to similar design rules.

Dr. Mii highlighted during TSMC's technology symposium that the N3 (3nm) process has received strong industry support and improves performance over the fab's first generation 5nm process. Image: TSMC 2021 Online Technology Symposium/Taiwan Semiconductor Manufacturing Company

Delving deeper into TSMC's progress with the N3 process node, Dr. Mii stated that 3nm would improve power consumption or performance over the first generation of its N5 family. The first generation N5 node is TSMC's 5nm process, which has already entered mass production. This process is followed by N4, which, compared to N5, offers a 6% smaller chip die, improves power consumption and performance and uses fewer masks during the production process. The usage of fewer masks hints that perhaps TSMC will increase EUV adoption with the newer process, and the executive also stated that N4 risk production will start in the third quarter of this year.

In an important disclosure, Dr. Mii stated that the N3 process has witnessed more than twice the tape-outs during its first year compared to the N5. A tape-out in the semiconductor industry refers to chip designers finalizing their designs before sending them over to a fab, which then either finetunes the design or moves towards production.

TSMC's SVP R&D Dr. Y.J. Mii outlined at its latest technology conference that it has managed to reduce voltage variation with its new nanosheet transistors. Image: TSMC 2021 Online Technology Symposium/Taiwan Semiconductor Manufacturing Company

While not explicitly tying TSMC's work on nanosheet transistors with its 2nm process, Dr. Mii shared key details for the circuits that might end up representing his company's most significant manufacturing jump in years. He outlined that nanosheet transistors have managed to implement tighter threshold voltage (Vt) control. In semiconductor design, Vt refers to the minimum voltage needed for a circuit to work, and even the slightest variations can introduce design constraints and performance drops.

According to the executive, the nanosheet transistors have managed to "demonstrate nanosheet transistors with more than 15% lower Vt variations as shown in blue compared to that of a very good FinFET transistor as shown in red."

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He proceeded to highlight his company's research with carbon nanotube transistors. TSMC's chairman, Dr. Mark Liu, focused on these transistors earlier this year at the ISSC 2021 conference, where he highlighted new material development as a key breakthrough in the area.

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