AMD Goes Bigger With EPYC Venice and Verano, with New SP7 and SP8 Sockets Dwarfing Today’s SP5 and SP6 Platforms

AMD's next-generation SP8 & SP7 sockets, designed for the Zen 6-powered EPYC Venice & Verano CPUs, have been detailed.

AMD SP8 & SP7 Sockets Are Bigger Than Their Predecessors, Showcasing The Compute Density Increase For Next-Gen EPYC Venice & Verano CPUs

Last year, AMD announced its EPYC Venice & EPYC Verano CPUs. The former comes with up to 256 cores in Zen 6C flavors with a launch scheduled for 2026, while the latter is a cost-effective Zen 6 offering that's slated for a 2027 launch.

Now, Taiwanese component manufacturer HELM Technology has revealed the new socket, each featuring a larger design than its predecessor. Starting with the SP7 socket, we are looking at a body size of 123.6 x 100.6mm, which is around 12% larger than the existing SP5 sockets that house EPYC Genoa & Turin CPUs. The socket retains the SRM (Socket Retention Mechanism) and features four layers: the SRM on top, a carrier board in the middle, the housing on the motherboard, and a backplate. The Housing contains the contact and solder balls that make contact with the CPU itself.

The second socket is SP8, which is designed for EPYC Verano CPUs. This is a more cost-effective offering based on the Zen 6 architecture, and features a slightly smaller 123.9 x 80.9mm footprint versus SP7, but is still 7% bigger than the previous generation SP6 socket. The main difference besides the larger body is that SP8 will also utilize the SRM load mechanism, while SP6 used a SAM (Socket Actuation Mechanism).

AMD SP7 Platform Features & Highlights

AMD's SP7 platform is going to go big with up to 16-channel DDR5 DRAM support that will feature up to 8000 MT/s ECC and 12,800 MT/s MRDIMMs in 1DPC configurations. It will also come with support for 1, 4, 8, 16, and 16-channel memory interleaves, and the types of memory supported by the platform will be expanded with RDIMM, 3DS RDIMM, MRDIMM, and Tall DIMM Dram solutions.

On the I/O side, the AMD SP7 platform will retain 2P support, so that's two next-gen sockets per motherboard and up to 128 PCIe Gen 6.0 lanes, offering 64 Gbps of bandwidth per lane. The SP7 platform will also offer up to 16 "Bonus" PCIe Gen 4 lanes. The single-socket "1P" version will get up to 96 PCIe Gen 6.0 lanes and 8 additional PCIe Gen 4 lanes. The platform will also support SDCI or Smart Data Cache Injection.

Summing up the platform, you are getting the following on AMD's SP7:

• Up To 16-Channel DDR5 Support
• Up To 8000 MT/s DDR5 ECC Memory
• Up To 12800 MT/s DDR5 RDIMM Memory
• Support for RDIMM, 3DS RDIMM, MRDIMM, Tall DIMM
• Up To 128 PCI Gen 6 + 16 PCIe Gen 4 Lanes on 2P Platform
• Up To 96 PCIe Gen 6 + 8 PCIe Gen 4 Lanes on 1P Platform

AMD SP8 Platform Features & Highlights

While the SP7 platform is meant for high-end enterprise and data center markets, SP8 will serve as the entry-level platform solution while retaining support for EPYC Verano chips. The platform will retain the same memory compatibility, but in 8-channel configurations. Interestingly, SP8 will offer more Gen 6.0 lanes versus SP7, with up to 192 PCIe Gen 6.0 lanes on 2P and 128 PCIe Gen 6.0 lanes on 1P platforms.

Summing up the platform, you are getting the following on AMD's SP8:

• Up To 8-Channel DDR5 Support
• Up To 8000 MT/s DDR5 ECC Memory
• Up To 12800 MT/s DDR5 RDIMM Memory
• Support for RDIMM, 3DS RDIMM, MRDIMM, Tall DIMM
• Up To 192 PCI Gen 6 + 16 PCIe Gen 4 Lanes on 2P Platform
• Up To 128 PCIe Gen 6 + 8 PCIe Gen 4 Lanes on 1P Platform

The AMD EPYC Venice Zen 6C or Zen 6 Dense chips will offer up to 32 cores per CCD, and there are a total of 8 CCDs, so that rounds up to the 256 core count figure. Each CCD will pack 128 MB of L3 cache for a total of 1024 or 1 GB of L3 cache on the full chip.

There are also two IO dies on the chip, with each featuring PCIe Gen 6.0 / CXL 3.1 functionality, and support for DDR5-8000 memory (interestingly, the diagram here lists the maximum MRDIMM speeds at 10,400 MT/s versus the 12,800 MT/s listed above), Gen4 Infinity Fabric, and Secure Processor.

The standard AMD EPYC "Venice" & "Verano" CPUs based on the classic Zen 6 cores will feature 12 cores per CCD. Each CPU houses eight CCDs with the same dual IO die configuration. These round up to 96 cores and 192 threads, so the same core count as the existing Turin offerings. Each CCD will get 48 MB of L3 cache, which is a 50% increase over the 32 MB L3 featured on Zen 5 chips.

• EPYC 9006 "Venice" With Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs / 1024 MB L3
• EPYC 9005 "Turin" With Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs / 384 MB L3
• EPYC 9006 "Venice" With Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs / 384 MB L3
• EPYC 9005 "Turin" With Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs / 384 MB L3

As per previous reports, the EPYC SP7 variants will feature TDPs of around 600W, up from 400W on Zen 5, and the SP8 chips will feature TDPs between 350- 400W. It should look like the following:

MD is upping its core count, compute capability, and IO features once again in a fantastic fashion. With EPYC Venice CPUs coming in 2026 and followed by Verano in 2027, we are in for exciting times for the data center segment.

News Source: @Olrak29_

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