AMD’s 6th Gen EPYC Venice “Zen 6 & Zen 6C” CPU Details Leak: Up To 8 CCDs, 96 “Classic” & 256 “Dense” Cores, 128 MB L3 Per CCD

First details of AMD's 6th Gen EPYC Venice CPUs based on the Zen 6 & Zen 6 core architectures have leaked & reports up to 256 cores.

AMD Pumps Out 256 Cores For Its Next-Gen EPYC Venice CPUs Featuring Zen 6 & Zen 6C Architectures, Up To Double The Cache Versus Turin

Reports surrounding the AMD 6th Gen EPYC Venice CPU platform have picked up the pace ever since Team Red confirmed that these will be the first chips to be made using TSMC's latest 2nm process technology. But the first details of these chips have been around since 2022, with more information being shared in 2023, so a good chunk of work has been out in the wild, and now, we have even more data from new leaks.

Based on previous reports, AMD's 6th Gen EPYC Venice CPUs will come in two flavors, just like the Zen 5 and Zen 4 offerings, a standard Zen 6 variant and a denser Zen 6C variant. These will be featured in the SP7 and SP8 sockets, with the former being the higher-end solution while the latter aims at the entry-level server solutions. The platform will come with both 16 & 12-channel memory support.

Now, coming to the juicy bits, there are several leaks reported in the Tieba Baidu forums, all of which point towards the alleged specs of the next-gen server powerhouses. First up, we have what seems to be a CCD layout of the chip featuring at least four CCDs on one side and four on the other, leading to a total of 8 CCDs. Each CCD packs 12 Zen 6 cores, and there are multiple IODs in the middle, which would lead to further expansion of I/O capabilities on these server platforms.

These round up to a total of 96 cores and 192 threads, which would be the same core counts as the current Zen 5-based Turin "EPYC 9005" offerings, but they are reported to pack up to 128 MB of L3 cache per CCD. It is not reported if the 128 MB L3 cache is for the Zen 6 or Zen 6C variants, but for a Zen 6C EPYC chip, which gives us 2 MB of L3 per core. As for the EPYC 9006 "Zen 6" SKUs, they will have up to 96 cores and 192 threads with up to 8 CCDs as reported above, while Zen 6C variants will scale up to 256 cores and 512 threads.

SP8: up to 128 Zen 6C cores with 128MB per CCD (96 cores for Zen 6 models), 350-400w

SP7: upto 256 Zen 6C cores, ~600w https://t.co/CQodEenhBk

— Bionic_Squash (@SquashBionic) May 10, 2025

Additional details come from Bionic_Squash, who reports that the SP7 variants will feature TDPs of around 600W, up from 400W on Zen 5, and the SP8 chips will feature TDPs between 350- 400W. It should look like the following:

• EPYC 9006 "Venice" With Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs
• EPYC 9005 "Turin" With Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs
• EPYC 9006 "Venice" With Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs
• EPYC 9005 "Turin" With Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs

The lineups will feature an extensive array of SKUs for data center and HPC customers to select from. These are still initial details, but Zen 6 is expected to launch sometime next year, so we are probably going to hear much more from Team Red in the coming time.

AMD EPYC CPU Families:

Family Name	AMD EPYC Verano	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	Zen 7	Zen 6	Zen 5	Zen 5C	Zen 5	Zen 4	Zen 4C	Zen 4 V-Cache	Zen 4	Zen 3	Zen 3	Zen 2	Zen 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCD's (1 CCX per CCD) + 2 IOD?	16 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1CCX per CCD) + 1 IOD	16 CCD's (1CCX per CCD) + 1 IOD	8 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (2 CCX's per CCD) + 1 IOD	4 CCD's (2 CCX's per CCD)
Memory Support	TBD	DDR5-12800	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W

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