TSMC’s Second Gen EUV 3nm Process Can Reduce Layers By 20% & Improve Gross Margin

A 300mm TSMC chip wafer on display at the 2020 World Semiconductor Conference in Nanjing, China. Image: Getty Images via Los Angeles Times

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According to a fresh report from Citigroup, the Taiwan Semiconductor Manufacturing Company (TSMC) is geared up for successive monthly revenue growth, removing the seasonality aspect of its business alongside significant cost reduction through the second generation of its leading-edge 3-nanometer chip fabrication process.TSMC is the world's leading contract chip manufacturer who is responsible for manufacturing semiconductors for big ticket tech firms such as Apple Inc, NVIDIA Corporation, Qualcomm Incorporated, with the company's successful partnership with Advanced Micro Devices, Inc (AMD) playing a crucial role in the latter's meteoric rise in the computing industry.

TSMC To Break Revenue Seasonality Through Consecutive Monthly Revenue Growth Until End Of This Year Believes Citigroup

The details, sourced by United Daily News (UDN), outlined that due to the strength of Apple's orders for its upcoming smartphone and the tight supply situation in the semiconductor industry, TSMC is set to grow revenue month-over-month for the remainder of this year. Due to the high demand for semiconductors from nearly every market segment, TSMC, who also navigated a water shortage earlier this year, is running at peak capacity, believes Citigroup.

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Today's report follows one which surfaced last week, in which the investment bank was highly optimistic about TSMC's future prospects. This report, followed by another one from JPMorgan, outlined that Citigroup expected the Taiwanese fab to earn $100 billion in revenue by 2025. According to JPMorgan, the catalysts to this growth, which estimates $100 billion in revenue in 2025, will primarily be high performance computing (HPC), which have seen their demand increase in the wake of the ongoing pandemic and will continue this trend in the future.

Citigroup outlines that due to the large orders from Apple and the current supply chain constraints in the chip sector, TSMC's older manufacturing process technologies, such as 7-nanometer (nm) and below, will also experience increased demand. Apple's focus is believed to be on the leading-edge 5nm process, which will play an integral role in the company's upcoming product lineup.


The high demand for nearly all of its manufacturing processes will result in TSMC posting consecutive revenue growth until the end of this year, according to Citi, especially since the incentive for companies to stockpile semiconductors is high due to the current supply chain situation.

Additionally, the bank also shared important information for TSMC's next-generation 3nm chip fabrication manufacturing process. A report from HSBC, which also surfaced last month, highlighted that TSMC's decision to increase semiconductor prices across the board would boost the company's gross margins. In financial terminology, the gross margin is the percentage of the company's earnings to its total revenue after the direct costs are removed.

It lets managers assess their cost efficiency, and the HSBC report outlined that following the price increase, TSMC's gross margins could sit anywhere between 53% to 55%. At the end of last year, the company's gross margin was 53%.

Now, Citigroup believes that TSMC's second generation 3nm process will further beef up the company's gross margin. It believes that by using extreme ultraviolet lithography (EUV), the fab will reduce layers on its semiconductors by nearly 20%. While this will not massively improve performance, it will let TSMC save up on manufacturing costs and, as a result, reduce the costs of manufacturing the advanced chips.

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EUV remains at the heart of the chip sector, with both TSMC and Santa Clara, California chip giant Intel Corporation aggressively focusing on the machines capable of using the light rays for chip fabrication. TSMC ships the bulk of the global chips manufactured with these machines, but the demanding nature of the chip sector will soon require access to even more advanced machines with wider lenses for accurately reproducing patterns on a silicon wafer.

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