With multiple supply chain reports focusing on Intel's EMIB-T chip packaging technology, analyst Ming-Chi Kuo has shared that TSMC's next-generation packaging technology, CoPoS, will enter mass production in 2028. CoPoS, short for chip-on-panel-on-substrate, seeks to overcome the limitations of the current CoWoS (chip-on-wafer-on-substrate) packaging technology by increasing the area on which the GPU, memory and other chips are mounted in an AI chip.
TSMC's CoPoS Packaging Technology Will Use Glass Core Sandwiched Between ABF As A Substrate, Says Analyst
With the demand for AI chips showing no signs of slowing down and Taiwan's TSMC continuing to be the only supplier of high-end chips, multiple supply chain reports have discussed Intel's EMIB-T packaging technology. Packaging an AI chip involves assembling its different components, such as the GPU and the memory, into a single unit, and reports have gone as far as to claim that NVIDIA is testing Intel's technology for its next-generation Feynman AI chips.
Now, Ming-Chi Kuo claims that Feynman might also be the first adopter of TSMC's next-generation packaging technology called CoPoS. TSMC currently relies on CoWoS packaging to serve the needs of high-end AI chip companies, with CoWoS' silicon interposer serving as a high-performant conduit of signals between the GPU and the memory of an AI chip.
Analyst Clarifies Key Misconceptions About TSMC's CoPoS Technology
The analyst claims that CoPoS will enter mass production in the second half of 2028, which is earlier than initially reported. One of the first adopters will be NVIDIA, and the technology will enable TSMC to manufacture larger packages, which are more than nine times larger than a standard stencil used in lithography.
In CoWoS packaging, a lithography machine is used to fabricate the interposer, which limits its size due to the stencil's size constraints. However, since CoPoS does not use an interposer, TSMC can make larger chip packages due to being able to manufacture larger panels that serve as an intermediary between the chip components and the organic package substrate.
According to Kuo, CoPoS uses glass first for the temporary carriers where the chip components are initially assembled and then the substrate where the final assembly is placed. This substrate, according to the analyst, is glass sandwiched between layers of Ajinomoto Buildup Film (ABF). The analyst adds that the technology does not use a glass interposer and the chips are attached to the ABF layer of the substrate.
About the author: Ramish is a seasoned technology writer and editor with more than a decade of experience. He specializes in semiconductor fabrication and market analysis. With a background in finance and supply chain management - via his bachelors in Finance and a micromasters in supply chain management from MIT - Ramish combines financial rigor with deep industry insight to deliver accurate and authoritative coverage.
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