It seems like the Taiwan giant won't be jumping onto the High-NA EUV bandwagon anytime soon. It has been revealed that the firm will skip the lithography for the A14 process.
TSMC Now Gets Behind The Likes of Intel Foundry When It Comes To High-NA EUV Adoption, Will Rely On Older Technologies
[Update]: We contacted TSMC to get a statement about the progress of High-NA EUV adoption, and here's what the Taiwan giant had to say:
TSMC carefully evaluates technology innovations such as new transistor structures and new tools and considers their maturity, cost, and benefit to customers before deploying them to volume production. TSMC plans to bring in high-NA EUV scanners first for R&D to develop the associated infrastructure and patterning solution needed for customers to fuel innovation.
- TSMC
When adopting newer elements in semiconductors, TSMC has been a pioneer for several years, and is often the trend-setter. But now, it seems like the firm will skip using the High-NA EUV lithography tool for its A14 process, as it will rely on the more conventional 0.33-NA EUV technology. This was revealed at the NA Technology Symposium, where TSMC's SVP Kevin Zhang announced the development (via Bits & Chips). With this, it is safe to say that Intel Foundry and several DRAM manufacturers now have a "technological" edge over TSMC.
TSMC will not be using high-NA EUV lithography to pattern A14 chips, manufacturing of which is scheduled to start in 2028. From 2 nanometers to A14, we don’t have to use high-NA, but we can continue to maintain similar complexity in terms of processing steps.
Each generation of technology, we try to minimize the number of mask increases. This is very important to provide a cost-efficient solution.
- TSMC's Kevin Zhang
Well, the primary reason why TSMC sees high-NA as something insignificant for the A14 process is that with the relevant lithography tools, the Taiwan giant could witness up to a 2.5x rise in costs compared to traditional EUV methods, and this will ultimately make the A14 node much more expensive to produce, which means that its adoption in consumer products would get difficult. The Taiwan giant is relying on chip designs and capabilities, but this certainly doesn't mean the company won't employ high-NA EUV for future processes, as it plans to utilize it for the A14P node.
One of the other reasons attributed to high-NA driving up costs is that TSMC's A14 would require multiple masks for a single layer of chip design, and using the latest lithography tools simply means the Taiwan giant is driving up costs without much benefit. Instead, by focusing on 0.33-NA EUV, TSMC can use multi-patterning techniques to maintain the same level of design complexity without needing the extreme precision of high-NA EUV, ultimately keeping production costs lower.
Interestingly, TSMC's decision to leave high-NA EUV behind does put the company behind the likes of Intel Foundry in adopting the latest tools, since Team Blue is said to utilize high-NA for the 18A process, which is expected to drop as soon as next year. With A14P targeted by 2029, TSMC would see at least a four-year delay in adopting high-NA compared to its counterparts, which could be a decision that can give competitors an edge.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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