AMD Ryzen 9 9950X3D 3D V-Cache CPU Review – The Ultimate Multi-Threading & Gaming Combo

The Zen 5 Architecture

It's been two years since AMD first introduced its AM5 platform alongside a brand new CPU family which we all know as Ryzen 7000 "Raphael". These chips brought in some impressive gains on the single and multi-threaded side of things while enabling higher efficiency than Intel's 13th & 14th Gen CPUs.

The company soon followed the launch with its new 3D V-Cache parts, the Ryzen 7000X3D family, which extended the SKUs range in the 12 and 16-core territory, offering another level of uplift for gamers. It's been more than a year since the launch of these parts and all eyes are on AMD's next-gen family, the Ryzen 9000 "Granite Ridge" Desktop CPUs.

AMD Ryzen 9000  'Zen 5' Desktop CPU Expected Features:

• Up To 16 Zen 5 Cores and 32 Threads
• Up To 16% IPC Improvement With Zen 5
• Brand New TSMC 4nm process node with 6nm IOD
• Up To 23% Faster Gaming Performance Versus Intel 14th Gen
• Up To 56% Faster Multi-Thread Performance Versus Intel 14th-gen
• Support on All Existing AM5 Platforms With LGA1718 Socket
• 800-Series Motherboard Introduction (X870E/X870)
• Faster Dual-Channel DDR5 Memory Support
• Up To DDR5-5600 Native (JEDEC) Speeds
• 28 PCIe Gen5 Lanes (CPU Exclusive / 24 Usable)
• 65W-170W TDPs

The AMD Ryzen 9000 Desktop CPU family, codenamed Granite Ridge, is based on the latest Zen 5 core architecture and targets high-performance Gaming PCs. The family is bringing a range of new features with the Zen 5 cores being the highlight while being supported on existing and upcoming AM5 platforms with improved I/O and DDR5 memory support.

AMD Zen 5 Core Architecture - Further Tweaking The Zen Architecture For A 16% IPC Uplift

So before we talk about the Ryzen 9000 Desktop CPU family, we first take a glance at the new and improved Zen 5 core architecture which offers:

• More Instructions delivered per cycle
• Improved branch prediction accuracy and latency
• Higher throughput with wider pipelines and vectors
• Deeper window size across the design for more parallelism
• Dispatch and execution expanded
• Doubled cache data bandwidth
• AI Acceleration

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In several aspects, the AMD Zen 5 core architecture offers up to a 2x increase such as the Instruction Bandwidth for the front-end instructions, data bandwidth (L2 to L1 and L1 to FP), and AI perf (AI & AVX512 Throughput). The Zen 5 CPU cores (CCDs) are based on the TSMC 4nm process node while the IOD is based on the TSMC 6nm process node. They come in the same peak config of 2 CCDs and 1 IOD on consumer platforms.

Zen 5 features a dual pipe fetch with an advanced branch prediction unit which enables:

• Branch Prediction: less latency, more accuracy, and throughput
• Instruction cache latency and bandwidth improvement
• Dual decode pipes

The Wider Dispatch & Execute Unit enables:

• 8-wide dispatch/retire
• 6 ALU, 3 multiples
• More unified ALU scheduler
• Large execution window

The increased data bandwidth is offered through:

• 48KB 12-way L1 data cache 4-cycle load
• Double the maximum bandwidth to the L1 cache and Floating Point Unit
• Improved data prefetching

And lastly, there's a 512-bit AI data path which offers:

• AVX-512 with full 512-bit data path
• 6 pipelines with two-cycle latency FADD
• A larger number of FP instructions in flight

These new changes have resulted in a significant IPC uplift averaging 16% versus Zen 4. In certain cases, the Zen 5 core can reach up to +35% IPC such as (Geekbench 5.4 AES XTS) and another key area that has been improved upon is the L2 and L3 cache structuring. AMD also made some significant changes to the IMC which now result in much higher EXPO/XMP memory support and the Infinity Fabric clock has been raised from 2000 MHz on Zen 4 to 2400 MHz on Zen 5 with DDR5-5600 speeds natively supported.

The updated AI engines such as the Math Acceleration Unit offer up to a 32% single-core performance uplift in Machine Learning and up to a 35% single-core improvement in AES-XTS instructions. According to AMD, the large majority of the Zen 5 uplifts come from the Execution/Retire unit, followed by the Decode/Opcache, Data Bandwidth, and Fetch/Branch Prediction (in order).

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