PCI-SIG Releases Final PCI Express 5.0 Specifications – Validated at 32 GT/s, Twice As Fast as PCI Express 4.0

PCI-SIG has released the final specifications of their new PCI Express 5.0 protocol which has been validated to deliver speeds of 32 GT/s. With the new PCI Express 5.0 protocol, we will be getting a 2x increase over PCI Express 4.0 which is an amazing feat considering that it took only 18 months to get here.

PCI-SIG Officially Announces PCI Express 5.0 Protocol, A 2x Bandwidth Improvement Over PCI Express 4.0

The announcement also comes with the release of the final specifications of the PCI Express 5.0 protocol which is rated to deliver a maximum bandwidth of 32 GT/s bit-rate. The link speed can scale up to 128 GT/s with an x16 link (64 GT/s on x8 and 48 GT/s on an x4 link). While there are some changes added to enhance the signal and mechanical performance, the PCI Express 5.0 protocol would remain backward compatible with PCIe 4.0, 3.0, 2.0 and 1.0 protocols too.

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Some feature highlights of PCI Express 5.0 include:

  • Delivers 32 GT/s raw bit rate and up to 128 GB/s via x16 configuration
  • Leverages and adds to the PCIe 4.0 specification and its support for higher speeds via extended tags and credits
  • Implements electrical changes to improve signal integrity and mechanical performance of connectors
  • Includes new backward-compatible CEM connector targeted for add-in cards
  • Maintains backward compatibility with PCIe 4.0, 3.x, 2.x and 1.x

“New data-intensive applications are driving demand for unprecedented levels of performance,” said Al Yanes, PCI-SIG Chairman, and President. “Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the foreseeable future.”

“For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next-generation systems, while preserving investments in prior generation interfaces and software,” noted Nathan Brookwood, a research fellow at Insight 64. “Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow. We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly.”


Some supporting quotes from industry leaders are mentioned below:


“AMD congratulates PCI-SIG on the release of the PCI Express 5.0 specification to the industry and the future 2x increase in performance it is expected to deliver. We expect to bring our first PCIe 4.0 specification CPUs to market this year and look forward to meeting the future bandwidth demands of end-users with PCIe 5.0 technology.”

~Gerry Talbot, AMD Corporate Fellow, Technology & Engineering Group, AMD

Astera Labs

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“Completed in under 2 years, PCI Express 5.0 technology is poised to quickly become the connectivity backbone in the next generation of servers. Astera Labs, a provider of innovative connectivity solutions, supports the new technology and emerging heterogeneous compute topologies with purpose-built signal conditioning products that enable robust PCIe 4.0 and PCIe 5.0 interconnects.”

~Sanjay Gajendra, Chief Business Officer, Astera Labs


“PCI-SIG’s announcement of the PCI Express 5.0 specification is a significant step that addresses the increasingly demanding requirements for compute and networking applications. The doubling of bandwidth to 32GT/s can significantly reduce the I/O bottleneck and bolster overall application performance. As an ongoing contributor to the development of the PCI Express specification, Cadence supports this latest release with complete, high-quality PHY and controller IP, and verification IP including the TripleCheck verification technology. This comprehensive Cadence offering allows customers to get to market faster with a robust, high-performance solution while reducing development costs and risk.”

~Amjad Qureshi, Corporate VP, R&D in the IP Group at Cadence Design Systems


Intel believes that open standards foster platform innovation, create healthy ecosystems, and accelerate market growth. As a founding promoter of PCI Express architecture, we fully support the newly-released PCIe 5.0 specification, and look forward to continuing the PCI Express specification tradition of high-performance, multi-platform, open interconnect.”

~Dr. Debendra Das Sharma, Intel Fellow, and Director of I/O Technology & Standards, Member of PCI-SIG® Board of Directors, Intel Corporation

Mellanox Technologies

“The exponential growth of data and the ever-increasing demands for higher data center performance, require the fastest data speeds between the compute, the interconnect and the storage infrastructures. The combination of Mellanox high-speed InfiniBand and Ethernet solutions, and PCI Express 5.0 technology, will empower the next generation of high-performance computing, artificial intelligence, cloud, database, storage and other applications.”

~Gilad Shainer, vice president of marketing, Mellanox Technologies


“PCI Express 5.0 technology will advance graphics and high-performance computing by doubling its bandwidth to approaching 64GB/s while maintaining socket compatibility with prior versions of the PCIe specification. We are proud to be part of the PCI-SIG team and look forward to the innovation that will be sparked by this next evolution.”

~Michael Diamond, senior director of strategic partnerships at NVIDIA and member of the PCI-SIG® board of directors, NVIDIA


“As an active member of the PCI-SIG for more than a decade, Synopsys has been heavily involved with helping to define the PCI Express 5.0 specification. By providing a complete DesignWare Controller, PHY, and Verification IP solution for PCIe 5.0 to the market early, we have already enabled many customers to successfully tape out their advanced 32 GT/s SoCs, with many more expected this year.”

~John Koeter, vice president of marketing for IP, Synopsys

Aside from artificial intelligence, machine learning, visual computing, storage and networking, gaming will also be a high-performance market application for PCI Express 5.0 however, PCI Express 4.0 just starting getting traction in the consumer market right now with the first platform supporting PCI Express 4.0 launching in the third quarter of 2019. Intel's leaked roadmaps show that PCI Express 5.0 support would be coming to their next-generation Sapphire Rapids Xeon platform but we can't say for the same for the consumer platforms. AMD is the first to PCIe 4.0 so we have to see who's the first to actually jump ship to Gen 5 with their consumer aimed HEDT & mainstream platforms.

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