Intel appears to have pulled out another card from its sleeve - the brand new Tremont architecture which marks the first major update since Bay Trail was released in 2013 and an architecture that will succeed Goldmont+. This will be the first 10nm process for this family of products and will be used in the Lakefield platform which brings the concept of Big.little cores (something smartphone tech enthusiasts would undoubtedly be aware of) to the x86 mobility product sphere. Mixing 'big' Sunny Cove and 'little' Tremont, Lakefield is set to offer a distinct upgrade over existing x86 setups today and will offer superior performance without the cost of battery life for mobility devices.
Intel Tremont architecture is the missing piece of the puzzle in its hybrid 3D Foveros
Here is what the official description for the Intel Tremont unveiling event at the Linley Fall processor conference reads:
The Tremont CPU architecture was designed for enhanced processing power in compact, low power packages. Products based on Tremont will span both client, IOT and Data Center products and combined with broader Intel portfolio of IPs Tremont will power a new generation of Intel products across the compute offering. This presentation will unveil, for the first time publicly, the details of the micro-architecture of Tremont as well as briefly touch on the implementation of Tremont with other Intel compute cores.
Intel's Tremont instruction set will feature a Core-standard branch prediction as well as 6 wide out of order instruction decode with 4 wide allocations. All of this will be connected by 10 execution ports and an L2 cache up to 4.5MB. The end product is a product that roughly offers Sandy Bridge level of performance in a highly mobile and portable package. Intel is focusing significantly on the single-thread performance this time and showed off some single-thread performance improvement graphs (SPECint* Rate base) relative to Goldmont Plus.
The performance hybrid part of the Tremont cores is something we have already tackled before in the Lakefield platform overview. The power/performance graphs definitely mirror Sunny Cove but features much higher power efficiency at much lower performance levels. The result is a core that will significantly improve battery life even when the "little" cores are engaged. Sunny Cove is set to be the biggest update in Intel's lineup and both of these products will be manufactured on the 10nm process.
What we know about Intel's Foveros and Lakefield
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Talking about the SOC itself and its individual layers, the Lakefield SOC that has been previewed consists of at least four layers or dies, each serving a different purpose. The top two layers are composed of the DRAM which will supplement the processor as the main system memory. This is done through the PoP (Package on Package) memory layout which stacks two BGA DRAMs on top of each other as illustrated in the preview video. The SOC won't have to rely on socketed DRAM in this case which saves a lot of footprint on the mainboard.
The second layer is the Compute Chiplet with a Hybrid CPU architecture and graphics, based on the 10nm process node. The Hybrid CPU architecture has a total of five individual Cores, one of them is labeled as the Big Core which features the Sunny Cove architecture. That's the same CPU architecture that will be featured on Intel's upcoming 10nm Ice Lake processors. The Sunny Cove Core is optimized for high-performance throughput. There are also four small CPUs that are based on the 10nm process but optimized for power efficiency.
The same die consists of Intel's Gen 11 graphics engine with 64 Execution Units. Last week, we got to see the performance of an Intel GT2 (Gen 11) Iris Plus 940 graphics chip with 64 Execution Units and the results were quite good compared to existing Intel Gen 9.5 graphics chips. You can check out the performance results here.
Knowing that the Lakefield SOC will feature the same graphics engine, we can expect a very decent graphics performance out of this 3D stacked processor. Then last of all is the base die which serves as the cache and I/O block of the SOC. Labeled as the P1222 and based on a 22FFL process node, the base die comes with a low cost and low leakage design while providing a feature-rich array of I/O capabilities.