With PCIe standards seeing massive upgrades, temperature concerns have been associated with the ever-growing transfer speeds expected in upcoming standards such as PCIe 6.0 and PCIe 7.0, but Intel has devised a unique fix.
To Combat High Temperatures Within Next-Gen PCIe 6.0 & PCIe 7.0 Links, Intel Presented A Unique Cooling Mechanism Which Involves PCIe Throttle Control
In a new Linux driver update, Intel has decided to address the temperature constraints associated with modern PCIe standards, such as PCIe Gen 6.0 & PCIe 7.0. Since mounting an active cooling solution on the PCIe interface itself isn't possible, the newest driver update downgrades the PCIe link speeds in case of high temperatures. You can call this thermal throttling to some extent, but in this case, it is for PCIe lanes.
This series adds PCIe bandwidth controller (bwctrl) and associated PCIe cooling driver to the thermal core side for limiting PCIe Link Speed due to thermal reasons. PCIe bandwidth controller is a PCI express bus port service driver. A cooling device is created for each port the service driver finds if they support changing speeds.
This series only adds support for controlling PCIe Link Speed. Controlling PCIe Link Width might also be useful but AFAIK, there is no mechanism for that until PCIe 6.0 (L0p) so Link Width throttling is not added by this series.
- Intel Engineer Ilpo Järvinen
The driver associates a "cooling device" with each PCIe link, through which speed manipulation is possible. In scenarios where temperatures go out of range, this device reduces the transfer speeds for the respective PCIe link, ultimately ensuring functionality. It is important to note that this implementation isn't associated with modern-day PCIe standards but is planned to be utilized for later standards, such as PCIe Gen 6.0, PCIe Gen 7.0, and beyond.
Well, this solution looks effective, but there might be performance concerns associated with it. However, we are still a long way ahead before this technique comes into implementation; hence, there's nothing to worry about for now. We might see some heat dissipation mechanism over a hardware level as well for future PCIe interfaces if the temperature problem persists on a wider level.
PCI-SIG recently unveiled the specifications for PCIe 7.0 which is expected to launch by 2025 and should see market adoption by 2027-2028 (servers first). The new standard is going to deliver up to 512 GB/s bandwidth and a 128 GT/s raw bit rate, doubling over PCIe 6.0 and quadrupling the rate of PCIe 5.0. As transfer speeds grow, we can expect new throttling mechanisms to be put in place to avoid overheating through these channels.
News Source: Phoronix
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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