Intel Emerald Rapids Xeon CPU Support Comes To LLVM 16 In Recent Project Commit

Jason R. Wilson
Intel Emerald Rapids Xeon CPU Support Comes To LLVM 16 In Recent Project Commit 1

In September, specifications for Intel Emerald Rapids, the 5th Generation of Xeon CPUs, leaked out, showing up to 64 cores, support for DDR5-5600, and more. Following the recent GCC patch that included the addition of support for Emerald Rapids comes the same support but for LLVM 16, the "collection of modular and reusable compiler and toolchain technologies."

Intel Emerald Rapids Xeon CPUs see inclusion into the recent commit for LLVM 16, due to release in March 2023

Michael Larabel, Editor for the Linux hardware site Phoronix reported that LLVM added the new support today with the new code section -march=emeraldrapids. Support for Raptor Lake and Meteor Lake was originally in the newly revised code but now includes the targeting for Emerald Rapids.

Throughout the LLVM 16 compiler's code, you can see references added for Emerald Rapids following the support for Sapphire Rapids. Larabel also notes that detection support is based on the section titled compiler-rt/lib/builtins/cpu_model.c, where for Emerald Rapids, the case 0xcf was added. This assigns the appropriate Intel processor model to the compiler.

Intel Emerald Rapids Xeon CPU Support Comes To LLVM 16 In Recent Project Commit 2

The other section is llvm/lib/TargetParser/Host.cpp, where the code locates the target processor's type and model.

Image source: LLVM.

Emerald Rapids is the successor to Sapphire Rapids and has recently started seeing additions from Intel into various open-source coding. Sierra Forest and Grand Ridge are additional Intel processor families that have seen inclusion into the code. Emerald Rapids is expected to be based on a variation of the 'Intel 7' node. This variation is expected to have a higher performance and frequency. The new Emerald Rapids will use the Raptor Cove core architecture. The architecture is optimized from the original Golden Cove core, expected to deliver up to ten percent IPC improvement over Golden Cove's cores. The new processor series will also have sixty-four cores across 128 threads.

The expected time frame for LLVM Compiler 16 to be released will be around March 2023, as long as there are no delays to the project. The commit was updated this morning, and for users interested in seeing the changes to the code, you can read the full commit on the LLVM Project's GitHub.

Intel Xeon SP Families (Preliminary):

Family BrandingSkylake-SPCascade Lake-SP/APCooper Lake-SPIce Lake-SPSapphire RapidsEmerald RapidsGranite RapidsDiamond Rapids
Process Node14nm+14nm++14nm++10nm+Intel 7Intel 7Intel 3Intel 3?
Platform NameIntel PurleyIntel PurleyIntel Cedar IslandIntel WhitleyIntel Eagle StreamIntel Eagle StreamIntel Mountain Stream
Intel Birch Stream
Intel Mountain Stream
Intel Birch Stream
Core ArchitectureSkylakeCascade LakeCascade LakeSunny CoveGolden CoveRaptor CoveRedwood Cove+?Lion Cove?
IPC Improvement (Vs Prev Gen)10%0%0%20%19%8%?35%?39%?
MCP (Multi-Chip Package) SKUsNoYesNoNoYesYesTBD (Possibly Yes)TBD (Possibly Yes)
SocketLGA 3647LGA 3647LGA 4189LGA 4189LGA 4677LGA 4677TBDTBD
Max Core CountUp To 28Up To 28Up To 28Up To 40Up To 56Up To 64?Up To 132?Up To 144?
Max Thread CountUp To 56Up To 56Up To 56Up To 80Up To 112Up To 128?Up To 264?Up To 288?
Max L3 Cache38.5 MB L338.5 MB L338.5 MB L360 MB L3105 MB L3120 MB L3?240 MB L3?288 MB L3?
Vector EnginesAVX-512/FMA2AVX-512/FMA2AVX-512/FMA2AVX-512/FMA2AVX-512/FMA2AVX-512/FMA2AVX-1024/FMA3?AVX-1024/FMA3?
Memory SupportDDR4-2666 6-ChannelDDR4-2933 6-ChannelUp To 6-Channel DDR4-3200Up To 8-Channel DDR4-3200Up To 8-Channel DDR5-4800Up To 8-Channel DDR5-5600?Up To 12-Channel DDR5-6400?Up To 12-Channel DDR6-7200?
PCIe Gen SupportPCIe 3.0 (48 Lanes)PCIe 3.0 (48 Lanes)PCIe 3.0 (48 Lanes)PCIe 4.0 (64 Lanes)PCIe 5.0 (80 lanes)PCIe 5.0 (80 Lanes)PCIe 6.0 (128 Lanes)?PCIe 6.0 (128 Lanes)?
TDP Range (PL1)140W-205W165W-205W150W-250W105-270WUp To 350WUp To 375W?Up To 400W?Up To 425W?
3D Xpoint Optane DIMMN/AApache PassBarlow PassBarlow PassCrow PassCrow Pass?Donahue Pass?Donahue Pass?
CompetitionAMD EPYC Naples 14nmAMD EPYC Rome 7nmAMD EPYC Rome 7nmAMD EPYC Milan 7nm+AMD EPYC Genoa ~5nmAMD EPYC BergamoAMD EPYC TurinAMD EPYC Venice

News Sources: Phoronix, LLVM Project GitHub page

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