In September, specifications for Intel Emerald Rapids, the 5th Generation of Xeon CPUs, leaked out, showing up to 64 cores, support for DDR5-5600, and more. Following the recent GCC patch that included the addition of support for Emerald Rapids comes the same support but for LLVM 16, the "collection of modular and reusable compiler and toolchain technologies."
Intel Emerald Rapids Xeon CPUs see inclusion into the recent commit for LLVM 16, due to release in March 2023
Michael Larabel, Editor for the Linux hardware site Phoronix reported that LLVM added the new support today with the new code section -march=emeraldrapids. Support for Raptor Lake and Meteor Lake was originally in the newly revised code but now includes the targeting for Emerald Rapids.
Throughout the LLVM 16 compiler's code, you can see references added for Emerald Rapids following the support for Sapphire Rapids. Larabel also notes that detection support is based on the section titled compiler-rt/lib/builtins/cpu_model.c, where for Emerald Rapids, the case 0xcf was added. This assigns the appropriate Intel processor model to the compiler.
The other section is llvm/lib/TargetParser/Host.cpp, where the code locates the target processor's type and model.
Emerald Rapids is the successor to Sapphire Rapids and has recently started seeing additions from Intel into various open-source coding. Sierra Forest and Grand Ridge are additional Intel processor families that have seen inclusion into the code. Emerald Rapids is expected to be based on a variation of the 'Intel 7' node. This variation is expected to have a higher performance and frequency. The new Emerald Rapids will use the Raptor Cove core architecture. The architecture is optimized from the original Golden Cove core, expected to deliver up to ten percent IPC improvement over Golden Cove's cores. The new processor series will also have sixty-four cores across 128 threads.
The expected time frame for LLVM Compiler 16 to be released will be around March 2023, as long as there are no delays to the project. The commit was updated this morning, and for users interested in seeing the changes to the code, you can read the full commit on the LLVM Project's GitHub.
Intel Xeon SP Families (Preliminary):
|Family Branding||Skylake-SP||Cascade Lake-SP/AP||Cooper Lake-SP||Ice Lake-SP||Sapphire Rapids||Emerald Rapids||Granite Rapids||Diamond Rapids|
|Process Node||14nm+||14nm++||14nm++||10nm+||Intel 7||Intel 7||Intel 3||Intel 3?|
|Platform Name||Intel Purley||Intel Purley||Intel Cedar Island||Intel Whitley||Intel Eagle Stream||Intel Eagle Stream||Intel Mountain Stream|
Intel Birch Stream
|Intel Mountain Stream
Intel Birch Stream
|Core Architecture||Skylake||Cascade Lake||Cascade Lake||Sunny Cove||Golden Cove||Raptor Cove||Redwood Cove+?||Lion Cove?|
|IPC Improvement (Vs Prev Gen)||10%||0%||0%||20%||19%||8%?||35%?||39%?|
|MCP (Multi-Chip Package) SKUs||No||Yes||No||No||Yes||Yes||TBD (Possibly Yes)||TBD (Possibly Yes)|
|Socket||LGA 3647||LGA 3647||LGA 4189||LGA 4189||LGA 4677||LGA 4677||TBD||TBD|
|Max Core Count||Up To 28||Up To 28||Up To 28||Up To 40||Up To 56||Up To 64?||Up To 132?||Up To 144?|
|Max Thread Count||Up To 56||Up To 56||Up To 56||Up To 80||Up To 112||Up To 128?||Up To 264?||Up To 288?|
|Max L3 Cache||38.5 MB L3||38.5 MB L3||38.5 MB L3||60 MB L3||105 MB L3||120 MB L3?||240 MB L3?||288 MB L3?|
|Memory Support||DDR4-2666 6-Channel||DDR4-2933 6-Channel||Up To 6-Channel DDR4-3200||Up To 8-Channel DDR4-3200||Up To 8-Channel DDR5-4800||Up To 8-Channel DDR5-5600?||Up To 12-Channel DDR5-6400?||Up To 12-Channel DDR6-7200?|
|PCIe Gen Support||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 4.0 (64 Lanes)||PCIe 5.0 (80 lanes)||PCIe 5.0 (80 Lanes)||PCIe 6.0 (128 Lanes)?||PCIe 6.0 (128 Lanes)?|
|TDP Range (PL1)||140W-205W||165W-205W||150W-250W||105-270W||Up To 350W||Up To 375W?||Up To 400W?||Up To 425W?|
|3D Xpoint Optane DIMM||N/A||Apache Pass||Barlow Pass||Barlow Pass||Crow Pass||Crow Pass?||Donahue Pass?||Donahue Pass?|
|Competition||AMD EPYC Naples 14nm||AMD EPYC Rome 7nm||AMD EPYC Rome 7nm||AMD EPYC Milan 7nm+||AMD EPYC Genoa ~5nm||AMD EPYC Bergamo||AMD EPYC Turin||AMD EPYC Venice|