In a surprising announcement, IBM introduced its 0.7-nanometer chip technology today to make it the first firm to have unveiled a manufacturing process smaller than the 1-nanometer technology node. The firm claims that the technology will enable chips to contain as much as 100 billion in an area the size of a fingernail. To achieve this, the technology relies on IBM's nanostack technology, which relies on nanosheets for chip fabrication.
IBM Makes Headway With Nanostack Chip Manufacturing Technology As Part Of 0.7 Nanometer Development
According to IBM, the 0.7-nanometer chip has nearly twice the density of its 2-nanometer chip unveiled in 2021. Back then, the firm had relied on nanosheet technology for the first time in a manufacturing process technology. IBM outlined that the 2-nanometer process had the capability to offer a 45% performance improvement or 75% lower power consumption over the most advanced 7-nanometer process technologies of the time.
Nanosheet technology with respect to chip manufacturing isn't a new development in the industry. A month after IBM's announcement, Taiwan's TSMC also discussed its nanosheet technology. At a symposium, TSMC's senior vice president of research and development, Dr. Yuh Jier Mii, outlined that the firm had managed to reduce voltage variation through its new nanosheet transistors.
The executive remarked that his firm had "demonstrate[d] nanosheet transistors with more than 15% lower Vt variations as shown in blue compared to that of a very good FinFET transistor as shown in red."
As part of its 0.7-nanometer announcement, IBM claims that the nanostack technology is an upgrade over the nanosheet technology. The firm outlines that nanostack, as the name suggests, vertically stacks and then staggers the transistors. This design approach enables 3D integration to pack more transistors on a chip, say the firm.
Additionally, the firm also outlined that the "nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration." The bonding requires precise alignment of the transistors.
Compared to the 2-nanometer chips, the 0.7-nanometer chips can deliver 70% higher power efficiency or a 50% performance improvement, says the firm.
IBM also outlines that an AI chip could increase its performance to 9,000 trillion operations per second from the current 4,500 TOPS through the 0.7 nanometer (7A) manufacturing technology to cut training time from three months to a couple of weeks.
The firm also shared more details about how it manufactured its nanostack transistors. According to IBM, it was able to develop "a new technique to bond two wafers to create a new, multilayered structure" to create 3D transistors that can lead to the development of next-generation computer chips.
About the author: Ramish is a seasoned technology writer and editor with more than a decade of experience. He specializes in semiconductor fabrication and market analysis. With a background in finance and supply chain management - via his bachelors in Finance and a micromasters in supply chain management from MIT - Ramish combines financial rigor with deep industry insight to deliver accurate and authoritative coverage.
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