Cadence System, the famous computing firm, has revealed the world's first 128GT/s PCIe 7.0 IP over optics, showing the potential encaptivated in the technology.
Cadence's Newest PCIe 7.0 IPs Target At Blazing Fast Speeds & Efficiencies, Being A Highlight At DevCon
[Press Release]: PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low-latency, non-retimed, linear optics connector.
We achieved and maintained a consistent, impressive pre-FEC BER of ~3E-8 (PCIe spec requires 1E-6) for the entire duration of the event, spanning over two full days with no breaks. This provides an ample margin for RS FEC. As seen in the picture below, the receiver Eye PAM4 histograms have good linearity and margin. This is the world’s first stable demonstration of 128 GT/s TX and RX over off-the-shelf optical connectors – by far the main attraction of DevCon this year.
As a leader in PCIe, our PCIe controller architect Anish Mathew shared his valuable insights on an important topic: "Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation. In summary, Cadence had a dominating presence on the demo floor with a record number of PCIe demos:
- PCIe 7.0 over optics
- PCIe 7.0 electrical
- PCIe 6.0 RP/EP interop back-to back
- PCIe 6.0 protocol in FLIT mode with Lecroy Exerciser (at Cadence booth)
- PCIe 6.0 protocol in FLIT mode (at the Lecroy booth)
- PCIe 6.0 JTOL with Anritsu and Tektronix equipment (at Tektronix booth)
- PCIe 6.0 protocol with Viavi Protocol Analyzer (at Viavi booth)
- PCIe 6.0 System Level Interop Demo with Gen5 platform (at SerialTek booth)
The Cadence team and its partners did a great job in coordinating and setting up the demos that worked flawlessly. This was the culmination of many weeks of hard work and dedication. Four different vendors featured our IP for PCIe 6.0. They attracted a lot of attention and drove traffic back to us.
News Source: Cadence
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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