AMD’s Zen 2 7nm CPU Core to Feature Double the L3 Cache Size
AMD’s next generation “Zen 2” core, which is slated for release some time next year, was a largely a mystery up until earlier in the month when the company took the covers off what its CPU engineering team has been cooking in its labs and it’s quite the tasty recipe!
Zen 2, despite its name, is actually going to power the company’s 3rd generation lineup of Ryzen processors. We have already seen the company’s 2nd generation product in the form of the 2000 series Ryzen lineup which brought us some algorithmic power and frequency fine tuning in addition to an improved FinFET process. With that being said, AMD does not consider 2nd generation Ryzen a redesign but rather a refinement of first generation Zen, which is expected to hold the line until 7nm is ready for prime-time next year.
AMD Zen 2 – Higher Clock Speeds, More IPC & Bigger Caches
We have already covered the bulk of new architectural improvements that AMD is bringing to the table with its next generation Zen 2 core built on TSMC’s 7nm process tech which you can find in the link above, however, here’s a refresher of some of the key enhancements:
- Improved Execution Pipeline
- Doubled Floating Point (256-bit) and Load/Store (Doubled Bandwidth)
- Doubled Core Density
- Half the Energy Per Operation
- Improved Branch Prediction
- Better Instruction Pre-Fetching
- Re-Optimized Instruction Cache
- Larger Op Cache
- Increased Dispatch / Retire Bandwidth
- Maintaining High Throughput for All Modes
And now, thanks to a leak on the SiSoft SANDRA database via TPU, we can also add double the L3 cache to that list. An entry for an upcoming ROME processor featuring the company’s Zen 2 core has popped up and it revealed that the 64 core chip actually features a whopping 256MB of L3 cache. That’s 16 MB per CCX, double that of the previous generation.
This indicates that we will likely see AMD debut 8 core mainstream Ryzen 3000 series processors with 32MB of L3 cache. A larger L3 means that the system would have to fetch data from DDR4 memory less often, which translates to faster work completion at less power. Undoubtedly contributing to the IPC and power efficiency gains that Zen 2 brings to the table compared to the original Zen design.
AMD CPU Roadmap (2018-2020)
|Ryzen Family||Ryzen 1000 Series||Ryzen 2000 Series||Ryzen 3000 Series||Ryzen 4000 Series||Ryzen 5000 Series|
|Architecture||Zen (1)||Zen (1) / Zen+||Zen (2)||Zen (3)||Zen (4)|
|Process Node||14nm||14nm / 12nm||7nm||7nm+||5nm/6nm?|
|High End Server (SP3)||EPYC 'Naples'||EPYC 'Naples'||EPYC 'Rome'||EPYC 'Milan'||EPYC 'Next-Gen'|
|Max Server Cores / Threads||32/64||32/64||64/128||TBD||TBD|
|High End Desktop (TR4)||Ryzen Threadripper 1000 Series||Ryzen Threadripper 2000 Series||Ryzen Threadripper 3000 Series (Castle Peak)||Ryzen Threadripper 4000 Series||Ryzen Threadripper 5000 Series|
|Max HEDT Cores / Threads||16/32||32/64||64/128?||TBD||TBD|
|Mainstream Desktop (AM4)||Ryzen 1000 Series (Summit Ridge)||Ryzen 2000 Series (Pinnacle Ridge)||Ryzen 3000 Series (Matisse)||Ryzen 4000 Series (Vermeer)||Ryzen 5000 Series|
|Max Mainstream Cores / Threads||8/16||8/16||16/32||TBD||TBD|
|Budget APU (AM4)||N/A||Ryzen 2000 Series (Raven Ridge)||Ryzen 3000 Series (Picasso 14nm Zen+)||Ryzen 4000 Series (Renior)||Ryzen 5000 Series|