AMD Officially Talks Zen 2 CPU Architecture: Significant Performance Uplift With 2X Throughput, Doubled Core Density With Up To 64 Cores, PCIe Gen 4.0 Support, Aiming Server EPYC Rome 7nm CPUs First
AMD has officially revealed the first details of their next-generation Zen 2 CPU architecture which will be used to power the upcoming EPYC Rome and Ryzen processors. Featured first on the EPYC Rome lineup, the new chips would be the first 7nm Datacenter processors, aiming for higher than expected IPC gains and overall improvement in total CPU performance.
AMD Zen 2 CPU Architecture Previewed – First 7nm Datacenter Products With Significant IPC Gains
With EPYC Rome, AMD skipped 10nm and went straight for 7nm. They have tapped in TSMC to produce the chips for them which gives them an edge over the previous partner, GloFo (Global Foundries). Following are some of the key points detailed for the 7nm process node:
- Major Node, Significant Investment
- Faster, Smaller, Lower Power Transistors (2x Density, 0.5x Power, 1.25x Performance at same performance/power)
- Multiple Products in Development
- Deep Partnership with TSMC and Design Automation Vendors
AMD has made significant changes to their CPU architecture which help deliver twice the throughput of their first generation Zen architecture. The major points include an entirely redesigned execution pipeline, major floating point advances with doubled the floating point to 256-bit and double bandwidth for load/store units. One of the key upgrades for Zen 2 is the doubling of the core density which means we are now looking at 2x the core count for each core complex (CCX).
- Improved Execution Pipeline
- Doubled Floating Point (256-bit) and Load/Store (Doubled Bandwidth)
- Doubled Core Density
- Half the Energy Per Operation
- Improved Branch Prediction
- Better Instruction Pre-Fetching
- Re-Optimized Instruction Cache
- Larger Op Cache
- Increased Dispatch / Retire Bandwidth
- Maintaining High Throughput for All Modes
Combining this breakthrough design methodology with the benefits of TSMC’s leading-edge 7nm process technology, “Zen 2” delivers significant performance, power consumption and density generational improvements that can help reduce datacenter operating costs, carbon footprint and cooling requirements. Other key generational advances over the award-winning “Zen” core include:
- An improved execution pipeline, feeding its compute engines more efficiently.
- Front-end advances – improved branch predictor, better instruction pre-fetching, re-optimized instruction cache and larger op cache.
- Floating point enhancements – doubled floating point width to 256-bit and load/store bandwidth, increased dispatch/retire bandwidth and maintained high throughput for all modes.
- Advanced security features – Hardware-enhanced Spectre mitigations, taking software migration and hardening it into the design, and increased flexibility of memory encryption.
Multiple 7nm-based AMD products are now in development, including next-generation AMD EPYC CPUs and AMD Radeon Instinct GPUs, both of which AMD detailed and demonstrated at the event. Additionally, the company shared that its follow-on 7nm+-based “Zen 3” and “Zen 4” x86 core architectures are on-track.
Zen 2 also includes stronger hardware level enhancements when it comes to security. This further solidifies AMD CPUs against enhanced Spectre variants and these mitigations will be adopted fully be Zen 2. When it comes to Zen, AMD already had strong software level support when it came to security and they have further enhanced it through low-level software mitigations.
AMD 2nd Generation EPYC ‘Rome’ – The Worlds First 7nm Datacenter CPU Family, Now With Double The Epicness!
With EPYC ‘Rome’, AMD is going all out, using several 7nm CPU chiplets (multiple CCX dies) based on their Zen 2 architecture that is connected with a 14nm I/O die that controls all of the memory, I/O and interconnects which the CPU dies can make direct access to.
AMD confirmed that the EPYC Rome series server processors would make use of eight 7nm CPU chiplets which will be connected to a large I/O die. The CPU chiplets will be able to house up to 64 cores and 128 threads. The EPYC Rome processors will also have access to faster 8 channel DDR4 memory lanes, allowing for higher bandwidth. This approach will allow for flexible future designs in the coming years while a separate die for I/O will enable faster memory and chip to chip access than before.
You can see below that there are indeed 8 chiplets in stacks of two. Each chiplet houses 8 cores and 16 threads. It is interesting to see the direction AMD is taking with EPYC as it tells a lot about where they will go with the mainstream consumer parts, especially the Ryzen 3000 series that will be using the same Zen 2 core architecture.
Some performance tidbits that AMD is sharing for their EPYC Rome server CPUs include:
- 2 Times The Performance Per Socket
- 4 Times The Floating Point Per Socket
For AMD’s first 7nm server family specifically, AMD made assumptions around Intel’s roadmap and what they would do if they were Intel. There’s no mystery about Intel’s next-generation Xeon CPUs as we know that the Skylake-SP (14nm+) chips will be replaced by the upcoming Cascade Lake-SP (14nm++) family and the recently announced Cascade Lake-AP (Advanced Performance) parts. We have quite a few details regarding the Cascade Lake-SP family which you can check out here but Forrest Norrod revealed some interesting details regarding Rome.
“Rome was designed to compete favorably with “Ice Lake” Xeons, but it is not going to be competing against that chip. We are incredibly excited, and it is all coming together at one point.” – Forrest Norrod. via TheNextPlatform
According to him, the AMD 7nm EPYC Rome processors were not designed to compete against the Cascade Lake-SP Xeon family, they were actually designed to compete favorably against Intel’s Ice Lake-SP Xeon processors. You heard it right folks, AMD’s 2019 CPU family is designed to tackle the Intel 10nm Ice Lake Xeons favorably and things are looking really good for AMD as their Rome CPU family will only be competing against Intel’s 14nm++ server refreshed family, aka Cascade Lake-SP. Intel’s Ice Lake-SP processors based on the 10nm process aren’t expected to arrive in the server Xeon space till 2020.
AMD Zen 4 CPU Architecture Nearing Design-Completion – Will Aim Post 2020 Launch
AMD also confirmed in their long-term roadmap that while Zen 2 7nm chips have started sampling now and Zen 3 7nm+ chips are on track for launch around 2020, they also have the new Zen 4 CPU architecture nearing design completion which will be featured in their post-2020 CPU products. It is a really interesting time for AMD with multiple strong products coming out and them finally getting back in action.
AMD CPU Roadmap (2018-2020)
|Ryzen Family||Ryzen 1000 Series||Ryzen 2000 Series||Ryzen 3000 Series||Ryzen 4000 Series||Ryzen 5000 Series|
|Architecture||Zen (1)||Zen (1) / Zen+||Zen (2)||Zen (3)||Zen (4)|
|Process Node||14nm||14nm / 12nm||7nm||7nm+||5nm/6nm?|
|High End Server (SP3)||EPYC 'Naples'||EPYC 'Naples'||EPYC 'Rome'||EPYC 'Milan'||EPYC 'Next-Gen'|
|Max Server Cores / Threads||32/64||32/64||64/128||TBD||TBD|
|High End Desktop (TR4)||Ryzen Threadripper 1000 Series||Ryzen Threadripper 2000 Series||Ryzen Threadripper 3000 Series (Castle Peak)||Ryzen Threadripper 4000 Series||Ryzen Threadripper 5000 Series|
|Max HEDT Cores / Threads||16/32||32/64||64/128?||TBD||TBD|
|Mainstream Desktop (AM4)||Ryzen 1000 Series (Summit Ridge)||Ryzen 2000 Series (Pinnacle Ridge)||Ryzen 3000 Series (Matisse)||Ryzen 4000 Series (Vermeer)||Ryzen 5000 Series|
|Max Mainstream Cores / Threads||8/16||8/16||16/32||TBD||TBD|
|Budget APU (AM4)||N/A||Ryzen 2000 Series (Raven Ridge)||Ryzen 3000 Series (Picasso 14nm Zen+)||Ryzen 4000 Series (Renior)||Ryzen 5000 Series|