With the release of AMD's new 3D V-Cache CPUs, many of us wondered why Team Red hadn't decided to use the additional cache on all the CCDs, and we now have an answer.
AMD Says Having 3D V-Cache Tiles On All CCDs Isn't Technically Impossible, But Is Financially Not Right
For those unaware, Team Red had recently launched its newest Zen 5 3D V-Cache CPU, featuring the Ryzen 9 9950X3D and the Ryzen 9 9900X3D, both of which feature a dual CCD (Core Chiplet Dies) layout. While AMD has managed to bring in decent performance gains to the new Zen 5 architecture, the firm, up till now, mounts the powerful 3D V-Cache on only one of its CCDs, and by potentially using the cache on both of the chiplet dies, Team Red can bring in more performance, but there's a twist here. HardwareLuxx managed to ask AMD about this, and here's what they had to say:
We asked AMD if there were any technical reasons why we haven't seen a Ryzen processor with two CCDs and a 3D V-Cache on each of the CCDs. The answer was surprising: there are no technical reasons or challenges.
Such a processor would simply be too expensive, and games would not benefit from a second CCD with a 3D V-Cache to the same extent as they would from the step from 32 to 96 MB L3 cache for one CCD.
- AMD via HardwareLuxx
Well, this means that integrating a dual 3D V-Cache onto the die isn't an issue for Team Red at all, but there are economic concerns. Additionally, with a dual 3D V-Cache system, thread scheduling will become a lot more inefficient, mainly because threads should remain on the cores with 3D V-Cache to leverage their full potential. With threads dynamically changing across both CCDs, this will ultimately not benefit Team Red.
Interestingly, AMD claimed it had tested a processor with a dual 3D V-Cache implementation but had decided against releasing it to the market. However, such CPUs could also pop up in the future, not for the consumer segment but for other applications where the financial costs outweigh the performance necessary to be brought in.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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