AMD EPYC Rome With 64 Zen Core 2 Cores Based on 7nm Technology Clock Speed Revealed – 2.35 GHz Inside The Hawk Supercomputer
It looks like the clock speeds for AMD’s EPYC Rome flagship have been revealed through a recent presentation for the new ‘Hawk’ supercomputer that is being developed by HLRS and HPE. Details of the clock speeds for AMD’s EPYC Rome chips are crucial since they will be the first outing of a high-performance 7nm process based chip for the HPC market.
AMD EPYC Rome With 64 Zen Core 2 Cores Based on 7nm Technology Clocks In At 2.35 GHz Inside Hawk Supercomputer
AMD did their first public unveiling of the EPYC Rome processors last week. A lot of details were revealed officially and I personally think that the 2nd Generation Rome chips are going to be a major dent in Intel’s Xeon / Server market share when they ship out next year based on cost and performance hints that we have received after the event concluded.
AMD only revealed one part at their presentation which featured 64 cores, arranged in eight 7nm chiplets (8 core die each), surrounding a large 14nm I/O die. The design is really revolutionary for the industry as it paves the way for cost-effective and high-performance solutions not only in the CPU market but also the GPU market. Details regarding the chip design were abundant, but AMD still left out the clock speeds, which will possibly be kept under wraps until the entire EPYC Rome family makes its formal debut sometime next year.
Now as far as the Hawk supercomputer is concerned, it will be packing the flagship AMD 64 core EPYC Rome processors which will be clocked at 2.35 GHz. Now, this is definitely an interesting clock speed, but we should go into more detail. We don’t know if this clock speed is a base clock or boost clock, but we can speculate a bit on this.
For starters, the current flagship EPYC 7601 clocks in at a base clock of 2.2 GHz and boosts all the way up to 3.2 GHz (1-core) and 2.7 GHz (all core). That part was based on the 14nm process node and featured 32 cores, 64 threads.
Here, we are talking about twice the cores and thread count. Usually, 3rd parties list the max clock speeds for a specific chip that they are going to use in their products. If the 2.35 GHz clock is for the base, it’s a good number considering the number of cores we are talking about. But here’s the thing, if 7nm clocks well, then this could very well be the base clock with a much higher boost frequency across single / all cores. In the latter case, AMD would just destroy the benchmarks with stellar IPC gains that are currently sitting around 28% (not entire workload based) over Zen+.
AMD CPU Roadmap (2018-2020):
|Ryzen Family||Ryzen 1000 Series||Ryzen 2000 Series||Ryzen 3000 Series||Ryzen 4000 Series|
|Architecture||Zen (1)||Zen (1) / Zen+||Zen (2)||Zen (3)|
|Process Node||14nm||14nm / 12nm||7nm||7nm+|
|High End Server (SP3)||EPYC 'Naples'||EPYC 'Naples'||EPYC 'Rome'||EPYC 'Milan'|
|Max Server Cores / Threads||32/64||32/64||64/128||TBD|
|High End Desktop (TR4)||Ryzen Threadripper 1000 Series||Ryzen Threadripper 2000 Series||Ryzen Threadripper 3000 Series (Castle Peak)||Ryzen Threadripper 4000 Series|
|Max HEDT Cores / Threads||16/32||32/64||32/64?||TBD|
|Mainstream Desktop (AM4)||Ryzen 1000 Series (Summit Ridge)||Ryzen 2000 Series (Pinnacle Ridge)||Ryzen 3000 Series (Matisse)||Ryzen 4000 Series (Vermeer)|
|Max Mainstream Cores / Threads||8/16||8/16||8/16||TBD|
|Budget APU (AM4)||N/A||Ryzen 2000 Series (Raven Ridge)||Ryzen 3000 Series (Picasso) Zen+?||Ryzen 4000 Series (Renior)|
AMD Zen 2 CPU Architecture Previewed – First 7nm Datacenter Products With Significant IPC Gains
With EPYC Rome, AMD skipped 10nm and went straight for 7nm. They have tapped in TSMC to produce the chips for them which gives them an edge over the previous partner, GloFo (Global Foundries). Following are some of the key points detailed for the 7nm process node:
- Major Node, Significant Investment
- Faster, Smaller, Lower Power Transistors (2x Density, 0.5x Power, 1.25x Performance at same performance/power)
- Multiple Products in Development
- Deep Partnership with TSMC and Design Automation Vendors
AMD has made significant changes to their CPU architecture which help deliver twice the throughput of their first generation Zen architecture. The major points include an entirely redesigned execution pipeline, major floating point advances with doubled the floating point word size to 256-bit and double bandwidth for load/store units. One of the key upgrades for Zen 2 is the doubling of the core density which means we are now looking at 2x the core count for each core complex (CCX).
- Improved Execution Pipeline
- Doubled Floating Point (256-bit) and Load/Store (Doubled Bandwidth)
- Doubled Core Density
- Half the Energy Per Operation
- Improved Branch Prediction
- Better Instruction Pre-Fetching
- Re-Optimized Instruction Cache
- Larger Op Cache
- Increased Dispatch / Retire Bandwidth
- Maintaining High Throughput for All Modes
Zen 2 also includes stronger hardware level enhancements when it comes to security. This further solidifies AMD CPUs against enhanced Spectre variants and these mitigations will be adopted fully be Zen 2. When it comes to Zen, AMD already had strong software level support when it came to security and they have further enhanced it through low-level software mitigations.
AMD confirmed that the EPYC Rome series server processors would make use of eight 7nm CPU chiplets which will be connected to a large I/O die. The CPU chiplets will be able to house up to 64 cores and 128 threads. The EPYC Rome processors will also have access to faster 8 channel DDR4 memory lanes, allowing for higher bandwidth. This approach will allow for flexible future designs in the coming years while a separate die for I/O will enable faster memory and chip to chip access than before.
You can see below that there are indeed 8 chiplets in stacks of two. Each chiplet houses 8 cores and 16 threads. It is interesting to see the direction AMD is taking with EPYC as it tells a lot about where they will go with the mainstream consumer parts, especially the Ryzen 3000 series that will be using the same Zen 2 core architecture.
Some performance tidbits that AMD is sharing for their EPYC Rome server CPUs include:
- 2 Times The Performance Per Socket
- 4 Times The Floating Point Per Socket
For AMD’s first 7nm server family specifically, AMD made assumptions around Intel’s roadmap and what they would do if they were Intel. There’s no mystery about Intel’s next-generation Xeon CPUs as we know that the Skylake-SP (14nm+) chips will be replaced by the upcoming Cascade Lake-SP (14nm++) family and the recently announced Cascade Lake-AP (Advanced Performance) parts. We have quite a few details regarding the Cascade Lake-SP family which you can check out here but Forrest Norrod revealed some interesting details regarding Rome.
“Rome was designed to compete favorably with “Ice Lake” Xeons, but it is not going to be competing against that chip. We are incredibly excited, and it is all coming together at one point.” – Forrest Norrod. via TheNextPlatform
According to him, the AMD 7nm EPYC Rome processors were not designed to compete against the Cascade Lake-SP Xeon family, they were actually designed to compete favorably against Intel’s Ice Lake-SP Xeon processors. You heard it, right folks, AMD’s 2019 CPU family is designed to tackle the Intel 10nm Ice Lake Xeons favorably and things are looking really good for AMD as their Rome CPU family will only be competing against Intel’s 14nm++ server refreshed family, aka Cascade Lake-SP. Intel’s Ice Lake-SP processors based on the 10nm process aren’t expected to arrive in the server Xeon space till 2020.