Intel EMIB-T Breaks Past Existing AI & HPC Scaling Limits, Enabling Ultra-Large Die Complexes With Over 10x Reticle Dies & 12 Gb/s+ HBM4e DRAM

Intel demonstrates the various use cases of its EMIB-T advanced packaging solution at ECTC26, as the tech is poised to become an industry favorite.

EMIB-T, Advanced Packaging Solution, Will Be Intel's Biggest Win To Data As Industry Faces Shortages & Limits In Existing Packaging Technologies

The era of advanced packaging solutions is in full swing, and there are only a few companies that offer the level of technical expertise and precision to make next-generation chips that are going to power AI, HPC and the Client segments.

At IEEE 2026 (ECTC), Intel demonstrated its next-generation packaging and substrate solution in full force. We have already seen Intel attract various customers for its EMIB advanced packaging solutions, such as TeraFab, Google, and NVIDIA, but EMIB-T has much wider implications in the manufacturing landscape.

The fundamental goal of EMIB is simple: to provide a high-speed and cost-effective interconnect that bridges multiple chiplets together.

EMIB has shown various advantages over TSMC's CoWoS packaging solutions, leading to more flexible and bigger compute architectures without worrying about costs and power. EMIB, as a silicon, is also much smaller than existing packaging techniques, leading to lower risks in chip manufacturing.

Intel Foundry’s Embedded Multi-die Interconnect Bridge with Through-silicon via (EMIB-T) technology [1] offers a scalable heterogeneous integration solution for chiplets because of its ability to combine the fine-pitch interconnect density of 2.5D integration with the vertical scaling benefits of through-silicon-via based architectures.

In this paper, we will present the scaling of the EMIB-T technology, specifically scaling the First Layer Interconnect (FLI) bump pitch down to 25 um and the package form factor size up to > 120 mm x 120 mm, which enables hosting more than 9x reticles of compute and memory silicon content on a single package. We will illustrate the achievable bandwidth densities resulting from this technology scaling and demonstrate that the electrical characteristics of EMIB-T enable reliable high-speed signaling exceeding 12 Gb/s for HBM4e. Finally, we will share the roadmap to enable future capabilities and new functionalities of EMIB-T, which will allow architects and designers to build a complete system on a single package to meet the future HPC/AI demands.

During the event, Intel and its partners showcased a whole slew of EMIB-T advanced packaging capabilities, which include the following:

3D Integration of an SRAM Chiplet in a Fan-Out Embedded Bridge Platform Achieving Low-Energy Read/Write

The ability to disaggregate large systems into chiplets using advanced packaging has provided an alternate path for continuing the scaling of state-of-the-art computer systems. In the context of memory systems, extending the memory capacity of a system with disaggregated memory chiplets requires a chiplet integration platform with high bandwidth connectivity and low energy overhead. Organic fan-out advanced packages such as fan-out embedded bridge can be leveraged to obtain a wide interconnect plane for 3D integration of memory chiplets.

In this paper, we demonstrate the 3D vertical integration of an SRAM chiplet embedded in a fan-out embedded bridge advanced package, achieving a bandwidth of 265 GB/s/mm2 at <0.24 pJ/bit in 50:50 read/write workloads. The embedded memory die is interconnected to a top die SoC through a dense microbump interconnect matrix with 25 µm pitch. An electrical analysis of the datapath reveals that the die-to-die connectivity accounts for less than 15% of the total power, while overall on-die data movement accounted for 30% of the total power.

A further reduction in energy per bit can be achieved at lower frequency, reaching 0.15 pJ/bit for an overall read/write bandwidth of 166 GB/s/mm2.This result demonstrates the feasibility of implementing memory functions in the embedded dies of organic packages and provides an additional design vector for system integration while meeting the modern system requirements for high bandwidth and low energy.

Enabling 12+Gb/s HBM4E with EMIB-T Advanced Packaging Technology

This paper presents a next-generation advanced packaging solution - Embedded multi-die interconnect bridge with through-silicon vias (EMIB-T), developed to meet the stringent bandwidth and power delivery requirements of cutting-edge HBM4E interfaces. The EMIB-T architecture incorporates a large number of metal layers, advanced routing capabilities, and integrated power delivery features.

Wideband electrical measurements and modeling correlations validate the superior signal and power delivery performance of the technology. We further demonstrate signal integrity and power integrity optimizations for HBM4E integration with EMIB-T, confirming the feasibility of 12+ Gb/s operation, establishing EMIB-T as a cost-effective and scalable advanced packaging solution for ultra-large die complexes with HBM4E memory stacks.

Package Architectures for Hyper Large Form-Factors for AI and HPC Segment

AI boom in the past few years has increased the demand for compute, resulting in need for larger silicon content per package. Additionally, integration of high bandwidth memory (HBM), network and other I/O tiles necessitates the need for heterogenous integration using advanced packaging. Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) with through silicon vias (TSVs) called EMIB-T provides a high bandwidth die-die and die-memory integration solution, with low power consumption, and the potential to scale to hyper large form factor (HLFF) package sizes (240 x 240 mm). This work describes the architectural considerations for designing packages up to the HLFF package sizes.

Package constructions with two configurations are proposed incorporating Application Specific Integrated Circuit (ASIC), HBM and I/O dies. Architecture and IP considerations using EMIB-T for 2 configurations are described. Subsequently, high speed I/O (HSIO) considerations for necessary performance for ASIC-ASIC, die-HBM bandwidth, 448G Serializer/De-serializer (SerDes) data rates and off package communication is explained. Power delivery solutions to meet required power integrity (PI) is described with on-package power noise decoupling schemes and voltage regulator options. Yield modeling is leveraged to delineate redundancy solutions, demonstrating design for yield. Thermal and thermo-mechanical design considerations are proposed to mitigate warpage driven challenges. Lastly, future scope for HLFF and AI packages are proposed.

Challenges and Solutions for Package-level Encapsulation of Ultra-large Die Complexes

High-performance computing and artificial intelligence workloads drive the demand for heterogeneous integrations of large number of compute, memory and I/O dies via advanced packaging, resulting in substantial growth in both the total die area on a package and the package form factor [1]-[3]. It introduces increasing difficulties for package-level encapsulation including long flow distance, voiding, keep-out-zone and package reliability. In this paper, the challenges of encapsulating ultra-large die complexes will be discussed first.

The unique difficulties for different advanced packaging architectures including 2.5D and 3D packaging will be explained. We will share innovative solutions in material formulation, equipment and process development to overcome the challenges and demonstrate the void-free process with several case studies including (1) 5X reticle die area based on EMIB, (2) >10X reticle die area base on EMIB, and (3) >4X reticle die area based on Foveros. The solution paths provide flexibility for various package architectures, and the final selection of the technology can be decided based on package design, throughput, cost and reliability requirements. Finally, we will share the future roadmap challenges and highlight the technical direction in technology development.

Key Differences of EMIB-M and EMIB-T

Currently, there are two key EMIB technologies: EMIB-M and EMIB-T. The EMIB-M bridge is designed for efficiency and features MIM capacitors in the silicon bridge that enhance power delivery and integrity by minimizing noise. Although slightly higher in costs versus Metal-Oxide-Metal capacitors, MIM or Metal-Insulator-Metal capacitors offer higher stability and lower leakage.

The building process of EMIB-M involves the creation of highly dense 3D structures through chiplets. The chiplets are connected via the EMIB-M bridge, which offers high-bandwidth interconnectivity. Power to the chiplets is routed around the bridge.

Embedded Multi-die Interconnect Bridge 2.5D.

• An efficient, cost-effective way to connect multiple complex dies.
• 2.5D packaging for logic-logic and logic-high-bandwidth memory (HBM).
• EMIB-M features MIM capacitors in the bridge. EMIB-T adds TSVs to the bridge.
• Silicon bridge embedded in package substrate for shoreline-to-shoreline connection.
• EMIB-T can ease the enablement of IP integration from other packaging designs.
• Simplified supply chain and assembly process.
• Production proven: In mass production since 2017 with Intel and external silicon.

This power routing is changed in EMIB-T, which offers scale-up density through the integration of TSVs. With EMIB-T, the power can be routed directly through the EMIB bridge rather than around the bridge, like in EMIB-M. EMIB-T is designed to fulfill the requirements of high-performance AI chips.

EMIB at Scale for the Hyperscaler Era

As of right now, EMIB-T offers chip scalability of >8x the reticle size in 120x120 packages, housing 12 HBM chips, 4 dense chiplets, and over 20 EMIB-T connections. By 2028, Intel plans to scale to >12x the reticle size in >120x180 packages housing over 24 HBM dies and over 38 EMIB-T bridges.

For comparison, TSMC is expected to reach 14x Reticle by 2028, incorporating up to 20 HBM packages. The company also has SoW (System of Wafer) packages for ultra-large advanced packaged chips, though those will come at a much higher cost than CoWoS.

A key advantage for EMIB is that its IP and process node agnostic, so you can house multiple chips based on various IPs and various 3rd party or internal process nodes, making chips that are built for bandwidth, power integrity, and scale.

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