AMD EPYC 9755 CPU Spotted: 128 “Zen 5” CPU Cores, 256 Threads, Up To 4.1 GHz Clocks & 650 MB of Cache

AMD's next-gen EPYC Turin CPU, the 9755, featuring an incredible 128 cores and 256 threads with a massive pool of cache has been spotted.

AMD EPYC 9755 "Turin" CPU Features 33% More High-Performance Cores Based on Zen 5 Architecture, A Huge Chunk of Cache

AMD's upcoming 5th Gen EPYC CPUs, codenamed Turin, are going to take core counts to the extreme. With up to 128 cores with the classic Zen 5 architecture and up to 192 cores with the density-optimized Zen 5C architecture. Both of these chips will go on to power the next-gen of data centers, offering big uplifts in performance.

While we have previously covered the full lineup along with actual engineering samples, it looks like one ES chip has been spotted by HXL (@9550pro) and well, it's a beast, to say the least. An alleged 64-core EPYC Turin CPU also leaked out a while ago with its performance benchmarks which you can see here. What you're looking at is the AMD EPYC 9755, one of the many SKUs within the Turin family.

This chip features 128 cores and 256 threads. You can see that the task manager is filled with columns upon columns of threads. Other details revealed by the source are 2.70 GHz base clocks and 4.10 GHz boost clock speeds. Now it is not mentioned if these are the final clocks but the current 4th Gen flagship, EPYC 9654, boosts up to 3.7 GHz so 4.10 GHz clock speeds are quite the uplift.

The other interesting aspect of this leaked CPU is that the AMD EPYC 9755 features a huge pool of cache. We are talking 512 MB or 1 GB of L3, 128 MB of L2, and 10 MB of L1 cache. This gives us a combined total of 650 MB of cache. The current EPYC 9654 CPU features just 384 MB of L3 cache and 96 MB of L2 cache.

We know that AMD's EPYC Turin "Zen 5" SKUs are composed of up to 16 CCDs while the "Zen 5C" SKUs are equipped with 8 CCDs. That would mean that each CCD packs 8 cores (16x8) and each CCD also packs 4 MB of L3 cache.

• EPYC 9755 "Zen 5" - 16 CCDs / 8 Cores Per CCD (128 Total) / 4 MB L3 Per Core (32 MB Per CCD) / 1 MB L2 Per Core (8 MB Per CCD) / 80 KB L1 Per Core (640 KB Per CCD) / 512 MB L3 + 128 MB L2 + 10 MB L1 = 650 MB Cache
• EPYC 9654 "Zen 4" - 12 CCDs/ 8 Cores Per CCD (96 Total) / 4 MB L3 Per Core (32 MB Per CCD) / 1 MB L2 Per Core (8 MB Per CCD) / 64 KB L1 Per Core (512 KB Per CCD) / 384 MB L3 + 96 MB L2 + 6 MB L1 = 496 MB Cache

Since this was a dual-socket configuration, there are 256 cores and 512 threads running in total with up to 1 GB of L3 cache, 256 MB of L2 cache, and 20 MB of L1 cache for a combined total of 1276 MB cache. This is a 31% uplift in cache sizes versus the previous Zen 4 flagships and we can only expect them to be massive once the 3D V-Cache "Turin-X" CPUs hit shelves next year.

AMD EPYC 9965

192c384t

500W TDP

— HXL (@9550pro) July 23, 2024

In addition to the EPYC 9755 CPU, HXL also posts details of another SKU, the 5th Gen EPYC 9965 which is based on the Zen 5C architecture and features 192 cores, 384 threads, and a TDP of 500 watts.

AMD is expected to launch its 5th Gen EPYC CPUs later this year which will compete with Intel's Xeon 6000P and Xeon 6000E families featuring 128 P-Cores and 288 E-Cores, respectively. This will be after a long time that Intel will have core-count parity with AMD's EPYC lineup so the rest would fall to which architecture has the best IPC, Efficiency, and overall performance.

AMD EPYC CPU Families:

Family Name	AMD EPYC Verano	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	Zen 7	Zen 6	Zen 5	Zen 5C	Zen 5	Zen 4	Zen 4C	Zen 4 V-Cache	Zen 4	Zen 3	Zen 3	Zen 2	Zen 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCD's (1 CCX per CCD) + 2 IOD?	16 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1CCX per CCD) + 1 IOD	16 CCD's (1CCX per CCD) + 1 IOD	8 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (2 CCX's per CCD) + 1 IOD	4 CCD's (2 CCX's per CCD)
Memory Support	TBD	DDR5-12800	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W

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