TSMC Begins 10nm FinFET Prototyping – Risk Production Scheduled for 2H 2016

Usman Pirzada
Posted Jul 7, 2015
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TSMC has produced the very first prototype chips on the 10nm process. These proof of concept chips will make  way for trial production of the pilot line, risk production and eventually volume production in the future. Currently, risk production of the 10nm process has been scheduled for sometime in 2H 2016. The process will be used in future low power circuits and eventually (after a very long time) high power circuits.

TSMC begins preliminary 10nm FinFET pilot line production

The existence of this validation vehicle for the 10nm node was revealed in the 52nd Design Automation Conference held recently and are critical to breaking the way for mass production on any scale. Their job is to make sure that all the electronic path ways, fabrication process and automation design software pass real life testing. Ofcourse, Intel is the only company in the world with a high performance sub 20nm node so the TSMC process will almost certainly target the low power market.

The proof of concept IC features an ARM Cortex-A57 module and the name for the process is CLN10FF+. The 10nm FinFet process can 110% more transistors than the 16nm FinFET+ process. Up to 20% higher clocks at the same power and 40% cut power consumption clock for clock. TSMC’s 10nm pilot line is being produced at its fab 15. This project is going to cost TSMC a cool 1 Billion dollars and will take several months to setup. Initital production is supposed to begin in late 2015. Q2 2016 will see TSMC construct a brand new foundry which will meet all the customers that 10nm FinFET attracts.

TSMC To Fully Adopt EUV For 5nm By 2020; 10nm To Be Profitable By End Of 2017

Ofcourse one of the biggest customers on the bleeding edge process market is Apple, and whoever gets to 10nm first will be able to seal the deal. As the largest contract manufacturer of wafers, TSMC has a much better chance than many, although Samsung is right on its heals. Intel does’t have any official plans as of yet and rumors indicate it will ramp as late as 2017 to 10nm. TSMC will also (fianlly) deploy EUV lithography that will eliminate the need for double pattering. Since the wavelength is 13.5nm, it is capable of printing designs upto 7nm natively and probably even below. Samsung Technology has also demonstrated 300mm wafers built on the 10nm node and plans to start high-volume production of semiconductors using 10nm fabrication process in 2016.

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